Abstract: The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.

Abstract: An embodiment of the invention provides a circuit for reducing power in memory cells. The input of the circuit is connected to the wordline of the memory cells. When the wordline is active, the output of the circuit applies a voltage near VDD to the positive voltage supply node of the memory cells. When the wordline is inactive, the output of the circuit applies a voltage that is reduced by at least one Vt from VDD to the positive voltage supply node of the memory cells.

Abstract: A system and method is disclosed for designing a dynamic circuit in a silicon-on-insulator (SOI) process comprising the steps of representing the dynamic circuit using at least one logic circuit, wherein the at least one logic circuit is selected from a group consisting of: an OR circuit with a DNG field effect transistor (FET), an OR circuit, and an AND circuit, and wherein the at least one logic circuit is selected according to body voltage characteristics of each circuit in the group.

Abstract: A system and method for generating dynamic circuit design guidelines is disclosed comprising modeling a dynamic circuit using one of a plurality of modeling circuit types, simulating the modeled dynamic circuit, extracting selected information from raw data measured during the simulating step, and analyzing the selected information to create the dynamic circuit design guidelines.

Abstract: A system and method is disclosed for designing a dynamic circuit in a silicon-on-insulator (SOI) process comprising the steps of representing the dynamic circuit using at least one logic circuit, wherein the at least one logic circuit is selected from a group consisting of: an OR circuit with a DNG field effect transistor (FET), an OR circuit, and an AND circuit, and wherein the at least one logic circuit is selected according to body voltage characteristics of each circuit in the group.

Abstract: A system and method for generating dynamic circuit design guidelines is disclosed comprising modeling a dynamic circuit using one of a plurality of modeling circuit types, simulating the modeled dynamic circuit, extracting selected information from raw data measured during the simulating step, and analyzing the selected information to create the dynamic circuit design guidelines.

Abstract: The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.

Abstract: During read operations of a column of RAM cells, a bitline is electrically broken into two sections. This reduces the capacitance that needs to be discharged by the RAM cell itself. A buffer is used during the read operation to relay data from one part of the split bitline to the other. A weak pullup path is also provided to hold the non-driven end of the line in a stable condition. During non-read operations, the two sections of bitline are electrically connected.

Abstract: A dynamic logic multiplexer has pull-ups on its input signals that pull-up the input signals when not selected. This reduces leakage current that may contribute to incorrect switching of the output. The output stage of the multiplexer includes a latched dynamic node followed by two gain stages, and an open-drain output.

Abstract: Logic is connected to the outputs of a dynamic logic gate to detect illegal or invalid states. The output of this detection logic sets a state catcher. The output of the state catcher is readable by scan logic so that the occurrence or non-occurrence of the invalid state may be read by test hardware.

Abstract: A data-shifting scheme is implemented where a group of arrays may be selected from a larger set of arrays. The arrays are connected to output-buffers and input-buffers such that data from the selected arrays may be read or written without changing addresses. The arrays are selected by programming the control signals controlling the output-buffers and input-buffers. The control signals may be programmed by several methods, for example, by blowing fuses or storing data in registers. The fuses do not have to be on pitch with the arrays. DRAMs, SRAMs, register arrays, and PLAs are examples of arrays that may be used with this invention. This invention is particularly useful for adding redundancy to an integrated circuit.

Abstract: An edge-triggered, self-resetting pulse generator where a pulse is initiated by a voltage transition and is reset using feedback from the output. A voltage transition is presented at one input of a two-input NOR gate and at the input of a circuit with three inverters in series. The output from the circuit with three inverters in series connects to the second input of the two-input NOR gate. This combination creates a voltage pulse that drives a transfer FET. The transfer FET creates a voltage on a latch. The latch stores the voltage presented on the input and then drives a delay-chain with an odd number of inverters. The output of the delay-chain drives a second transfer FET that resets the latch.

Abstract: A circuit and method characterizes a sense amplifier, such as the type utilized in computer memory systems. The sense amplifier characterization circuit comprises a sense amplifier having one or more inputs and an output, a BIT line connected to one of the one or more inputs of the sense amplifier, a register connected to the output of the sense amplifier; and control logic connected to the BIT line. Optionally, the register is further connected to the control logic, and the register is a scan register connectable to a tester. Preferably, the sense amplifier is a differential sense amplifier, and the circuit further comprises a complement BIT line connected to one of the one or more inputs of the sense amplifier. The method produces one or more signals like an output of a memory cell, operates one or more sense amplifier to produce one or more output states on the basis of the one or more signals, and records the one or more output states.

Abstract: A content addressable memory, CAM, cell wherein the only compare-transfer FETS used are NFETs. The gates of the NFET compare-transfer FETS are driven to a voltage above the positive power supply, VDD. By precharging the bitlines to the negative power supply voltage, GND, the gate of one of the compare-transfer NFETS is driven above VDD when a bitline transitions from a “low” value to a “high” value. The capacitance between the bitline being driven high and the gate of a compare-transfer NFET couples the gate higher than VDD. This bootstrapping technique improves the compare access time of a CAM. In addition, this technique reduces the capacitance on the bitlines resulting in faster read and write access times and reduces the physical size of the CAM.

Abstract: A decoder circuit in a memory system accepts as inputs a clock signal and a plurality of address lines and produces as outputs a plurality of decode lines, such as word lines. The decoder circuit comprises a plurality of pre-decoding circuits, a plurality of latches, and a plurality of AND gates. Each pre-decoding circuit is connected to the clock signal and a unique combination of a subset of the plurality of address lines and their complements. Each pre-decoding circuit produces an output that is set in response to a unique state of the respective subset of the plurality of address lines. Each latch input is connected to an output of a respective one of the plurality of pre-decoding circuits. Each latch output is connected to an AND gate input, and each AND gate output is one of the plurality of decode lines. In another sense, the decoder comprises one or more stages of decoding logic and a set of latches. A first stage of decoding logic accepts the decoder inputs.

Abstract: An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two transistors are pass transistors. The inverters are cross-coupled, through the variable resistors, to form a flip flop circuit which stores binary logic states. The variable resistors are formed by doping a portion of a polysilicon layer. Above the doped polysilicon resistor is a thin oxide layer. Disposed above the oxide layer is a thin layer of aluminum or polysilicon, which is connected by metallization. When a positive voltage is applied to the metallization, electrons accumulate in the doped polysilicon resistor, thereby lowering the resistance value of the polysilicon region. This voltage is applied to the interconnect during a write-in cycle, when it is desired to write data to the SRAM cell. The lowered resistance value of the polysilicon resistor allows for relatively fast write-in times for the SRAM cell.