Abstract: A circuit includes at least three equally weighted drivers; a state variable generator; and an element selector. The latter is coupled to the drivers, has a first input from the generator, has a second input including a plurality of input thermometer-encoded data streams, and has an output of an equal number of thermometer-encoded output data streams supplied to the drivers. The element selector maps the second input to the output dynamically based on a value of the first input from the state variable generator, with an update rate that is no more than one half of a symbol-rate. A serializer is configured to provide serialized data at the symbol rate, with output coupled to one of the second input of the element selector and input of the drivers. The drivers have outputs that are combined to produce an output of the circuit at the symbol rate.

Abstract: A circuit includes at least three equally weighted drivers; a state variable generator; and an element selector. The latter is coupled to the drivers, has a first input from the generator, has a second input including a plurality of input thermometer-encoded data streams, and has an output of an equal number of thermometer-encoded output data streams supplied to the drivers. The element selector maps the second input to the output dynamically based on a value of the first input from the state variable generator, with an update rate that is no more than one half of a symbol-rate. A serializer is configured to provide serialized data at the symbol rate, with output coupled to one of the second input of the element selector and input of the drivers. The drivers have outputs that are combined to produce an output of the circuit at the symbol rate.

Abstract: A multiply-accumulate device comprises a digital multiplication circuit and a mixed signal adder. The digital multiplication circuit is configured to input L m1-bit multipliers and L m2-bit multiplicands and configured to generate N one-bit multiplication outputs, each one-bit multiplication output corresponding to a result of a multiplication of one bit of one of the L m1-bit multipliers and one bit of one of the L m2-bit multiplicands. The mixed signal adder comprises one or more stages, at least one stage configured to input the N one-bit multiplication outputs, each stage comprising one or more inner product summation circuits; and a digital reduction stage coupled to an output of a last stage of the one or more stages and configured to generate an output of the multiply-accumulate device based on the L m1-bit multipliers and the L m2-bit multiplicands.

Abstract: A multiply-accumulate device comprises a digital multiplication circuit and a mixed signal adder. The digital multiplication circuit is configured to input L m1-bit multipliers and L m2-bit multiplicands and configured to generate N one-bit multiplication outputs, each one-bit multiplication output corresponding to a result of a multiplication of one bit of one of the L m1-bit multipliers and one bit of one of the L m2-bit multiplicands. The mixed signal adder comprises one or more stages, at least one stage configured to input the N one-bit multiplication outputs, each stage comprising one or more inner product summation circuits; and a digital reduction stage coupled to an output of a last stage of the one or more stages and configured to generate an output of the multiply-accumulate device based on the L m1-bit multipliers and the L m2-bit multiplicands.

Abstract: Techniques that facilitate control of dual phase tuners are provided. In one example, a system includes a first phase tuner and a second phase tuner. The first phase tuner is driven to a first phase bias that is different than a desired phase bias for an interferometer. The second phase tuner is driven to a second phase bias. A combination of the first phase bias and the second phase bias corresponds to the desired phase bias.

Abstract: Methods and systems of performing feed forward equalization (FFE) on data streams are described. A circuitry may generate staggered data streams from data streams of an input signal. The staggered data streams may include data in staggered unit intervals. The circuitry may include a plurality of segments. A segment may define a specific unit interval to carve the staggered data streams into one unit interval pulses positioned at the specific unit interval. The specific unit interval to carve the staggered data streams may indicate an assignment of the segment as one of a FFE pre tap, a FFE main tap, and a FFE post tap. The plurality of segments may be assigned to different FFE taps based on different clock signal selection defining different unit intervals to perform the carving. The plurality of segments may output respective one unit interval pulses to reproduce the input signal.

Abstract: Techniques that facilitate control of dual phase tuners are provided. In one example, a system includes a first phase tuner and a second phase tuner. The first phase tuner is driven to a first phase bias that is different than a desired phase bias for an interferometer. The second phase tuner is driven to a second phase bias. A combination of the first phase bias and the second phase bias corresponds to the desired phase bias.

Abstract: A neural signal recording device includes a scan-mode circuit and a read-mode circuit. The scan-mode circuit detects neural spike activity within any M groups of electrodes selected from a total of N electrodes that are coupled to a brain. The read-mode circuit then records all neural spike signals present within any one of the M groups of electrodes where the neural spike activity is detected by the scan-mode circuit, whereby less than N electrodes are recorded at any one time by the neural signal recording device.

Abstract: P and N termination networks couple a P line and an N line to corresponding receiver inputs. Each termination network includes an electrostatic discharge protection T-coil having an input port coupled to the corresponding line, a terminal port, and a center tap port. At least one of the termination networks further includes at least one delay T-coil having a terminal port, a center tap port, and an input port coupled to the terminal port of a corresponding one of the electrostatic discharge protection T-coils. In a no delay mode, a multiplexer selectively connects the P and N electrostatic discharge protection T-coil center tap ports to the P and N inputs of the receiver. In a delay mode, the multiplexer selectively connects the delay T-coil center tap port to a corresponding one of the P input of the receiver and the N input of the receiver.

Abstract: An integrated circuit includes a degeneration network configured to improve group delay across one or more variations, wherein the degeneration network includes a transimpedance amplifier with one or more degeneration inductors. The transimpedance amplifier further includes one or more transistors, and the one or more degeneration inductors are connected after at least one emitter of the one or more transistors.

Abstract: A device and method of optical equalization using an optical modulator is provided. An electrical modulation signal is split into a first modulation signal and a second modulation signal. The second modulation signal is delayed relative to the first modulation signal. An amplitude of the second modulation signal is attenuated relative to the first modulation signal. The first modulation signal is applied to a first waveguide segment of the optical modulator. The second modulation signal that is delayed and attenuated relative to the first modulation signal is applied to a second waveguide segment of the optical modulator. Both the applied first and second modulation signals generate a feed-forward equalized optical signal that is recombined in the optical domain.

Abstract: Methods and systems of performing feed forward equalization (FFE) on data streams are described. A circuitry may generate staggered data streams from data streams of an input signal. The staggered data streams may include data in staggered unit intervals. The circuitry may include a plurality of segments. A segment may define a specific unit interval to carve the staggered data streams into one unit interval pulses positioned at the specific unit interval. The specific unit interval to carve the staggered data streams may indicate an assignment of the segment as one of a FFE pre tap, a FFE main tap, and a FFE post tap. The plurality of segments may be assigned to different FFE taps based on different clock signal selection defining different unit intervals to perform the carving. The plurality of segments may output respective one unit interval pulses to reproduce the input signal.

Abstract: Methods according to the disclosure include methods for managing data flow in an optical communications system having a plurality of vertical cavity surface emitting lasers (VCSELs). The method generally includes determining whether operation of the system exceeds a thermal threshold for a thermal parameter of the system, and switching from a first data bandwidth to a second data bandwidth when the thermal threshold is exceeded. Operation at the second data bandwidth further includes determining whether further operation of the system demands the first data bandwidth, and resuming operation of the system at the first data bandwidth only when the thermal parameter during operation at the second data bandwidth does not exceed the thermal threshold.

Abstract: Methods according to the disclosure include methods for controlling an optical communications system. The method may include adjusting a VCSEL transmitter of the optical communications system to operate at a second data bandwidth distinct from its first data bandwidth; reducing a data flow rate of a receiver during operation of the optical communications system at the second data bandwidth; determining whether a system quality metric for the receiver meets a specification requirement; in response to determining the system quality metric does not meet the specification requirement, adjusting an operational setting of the VCSEL transmitter or the receiver; in response to determining the system quality metric meets the specification requirement, continuing operation of the optical communications system at the second data bandwidth; and in response to receiving an override signal, resuming operation of the optical communications system at the first data bandwidth.

Abstract: A neural signal recording device includes a scan-mode circuit and a read-mode circuit. The scan-mode circuit detects neural spike activity within any M groups of electrodes selected from a total of N electrodes that are coupled to a brain. The read-mode circuit then records all neural spike signals present within any one of the M groups of electrodes where the neural spike activity is detected by the scan-mode circuit, whereby less than N electrodes are recorded at any one time by the neural signal recording device.

Abstract: Methods according to the disclosure include methods for managing data flow in an optical communications system having a plurality of vertical cavity surface emitting lasers (VCSELs). The method generally includes determining whether operation of the system exceeds a thermal threshold for a thermal parameter of the system, and switching from a first data bandwidth to a second data bandwidth when the thermal threshold is exceeded. Operation at the second data bandwidth further includes determining whether further operation of the system demands the first data bandwidth, and resuming operation of the system at the first data bandwidth only when the thermal parameter during operation at the second data bandwidth does not exceed the thermal threshold.

Abstract: An integrated circuit includes a degeneration network configured to improve group delay across one or more variations, wherein the degeneration network includes a transimpedance amplifier with one or more degeneration inductors. The transimpedance amplifier further includes one or more transistors, and the one or more degeneration inductors are connected after at least one emitter of the one or more transistors.

Abstract: An integrated circuit includes a degeneration network configured to improve group delay across one or more variations, wherein the degeneration network includes a transimpedance amplifier with one or more degeneration inductors. The transimpedance amplifier further includes one or more transistors, and the one or more degeneration inductors are connected after at least one emitter of the one or more transistors.

Abstract: A device and method of optical equalization using an optical modulator is provided. An electrical modulation signal is split into a first modulation signal and a second modulation signal. The second modulation signal is delayed relative to the first modulation signal. An amplitude of the second modulation signal is attenuated relative to the first modulation signal. The first modulation signal is applied to a first waveguide segment of the optical modulator. The second modulation signal that is delayed and attenuated relative to the first modulation signal is applied to a second waveguide segment of the optical modulator. Both the applied first and second modulation signals generate a feed-forward equalized optical signal that is recombined in the optical domain.

Abstract: A device and method of optical equalization using an optical modulator is provided. An electrical modulation signal is split into a first modulation signal and a second modulation signal. The second modulation signal is delayed relative to the first modulation signal. An amplitude of the second modulation signal is attenuated relative to the first modulation signal. The first modulation signal is applied to a first waveguide segment of the optical modulator. The second modulation signal that is delayed and attenuated relative to the first modulation signal is applied to a second waveguide segment of the optical modulator. Both the applied first and second modulation signals generate a feed-forward equalized optical signal that is recombined in the optical domain.