Patents by Inventor Jonathan Eastep

Jonathan Eastep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11809250
    Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Ali Mohammad, Asma Al-Rawi, Ujjwal Gupta, Federico Ardanaz, Jonathan Eastep
  • Publication number: 20210124404
    Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 29, 2021
    Applicant: Intel Corporation
    Inventors: Ali Mohammad, Asma Al-Rawi, Ujjwal Gupta, Federico Ardanaz, Jonathan Eastep
  • Patent number: 10908668
    Abstract: Systems, apparatuses and methods may provide for determining, from a program comprising graphs of parallel operations and dependencies, an estimation of a droop risk associated with execution of the graphs by a load. A risk signal may be outputted based on the estimation. The risk signal may be associated with an adjustment in an output voltage of a voltage regulator and the output voltage is to be provided to the load.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Fuat Keceli, Jonathan Eastep, Kelly Livingston, Federico Ardanaz
  • Patent number: 10684663
    Abstract: Systems, apparatuses and methods may provide for receiving indicator data associated with activity of a load. Additionally, an estimation of a rate of change of a current of the load with respect to time may be determined from the indicator data. Moreover, a boost signal may be selectively output to a voltage regulator when the estimation of the rate of change is greater than a first amount. The boost signal may be associated with an adjustment in an output voltage of the voltage regulator and the output voltage may be provided to the load.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Kelly Livingston, Federico Ardanaz, Dmitry Lukianchenko, Fuat Keceli, Jonathan Eastep
  • Publication number: 20190044883
    Abstract: In multi-processor systems, some large jobs are performed by dividing the job into multiple tasks, having each task executed in parallel by separate nodes, and combining or synchronizing the results into a final answer. When communications between nodes represent a significant portion of total performance, techniques may be used to monitor and balance communications between the nodes so that the tasks will be completed at approximately the same time, thereby accelerating the completion of the job and avoiding wasting time and power by having some processors sit idle while waiting for other processors to catch up. Multiple synchronization points may be set up between the start and finish of task execution, to that mid-course corrections may be made.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Janusz Piotr Jurski, Jonathan Eastep, Keith D. Underwood, Madhusudhan Rangarajan
  • Publication number: 20190041930
    Abstract: Systems, apparatuses and methods may provide for receiving indicator data associated with activity of a load. Additionally, an estimation of a rate of change of a current of the load with respect to time may be determined from the indicator data. Moreover, a boost signal may be selectively output to a voltage regulator when the estimation of the rate of change is greater than a first amount. The boost signal may be associated with an adjustment in an output voltage of the voltage regulator and the output voltage may be provided to the load.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Kelly Livingston, Federico Ardanaz, Dmitry Lukianchenko, Fuat Keceli, Jonathan Eastep
  • Publication number: 20190041942
    Abstract: Systems, apparatuses and methods may provide for determining, from a program comprising graphs of parallel operations and dependencies, an estimation of a droop risk associated with execution of the graphs by a load. A risk signal may be outputted based on the estimation. The risk signal may be associated with an adjustment in an output voltage of a voltage regulator and the output voltage is to be provided to the load.
    Type: Application
    Filed: December 29, 2017
    Publication date: February 7, 2019
    Inventors: Fuat Keceli, Jonathan Eastep, Kelly Livingston, Federico Ardanaz
  • Patent number: 10048738
    Abstract: Apparatus and methods may provide for a central power control unit to grant a power allowance to each of a plurality of computer components and to allocate a shared power pool locally accessible to each of the plurality of computer components when one or more of the plurality of components needs to exceed its granted power allowance.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Federico Ardanaz, Jonathan Eastep, Richard Greco
  • Publication number: 20170255247
    Abstract: Apparatus and methods may provide for a central power control unit to grant a power allowance to each of a plurality of computer components and to allocate a shared power pool locally accessible to each of the plurality of computer components when one or more of the plurality of components needs to exceed its granted power allowance.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 7, 2017
    Applicant: Intel Corporation
    Inventors: Federico Ardanaz, Jonathan Eastep, Richard Greco