Patents by Inventor Jonathan Elliot Bergsagel
Jonathan Elliot Bergsagel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230350811Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Inventors: Sriramakrishnan GOVINDARAJAN, Gregory Raymond SHURTZ, Mihir Narendra MODY, Charles Lance FUOCO, Donald E. STEISS, Jonathan Elliot BERGSAGEL, Jason A.T. JONES
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Patent number: 11693787Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.Type: GrantFiled: February 9, 2021Date of Patent: July 4, 2023Assignee: Texas Instruments IncorporatedInventors: Sriramakrishnan Govindarajan, Gregory Raymond Shurtz, Mihir Narendra Mody, Charles Lance Fuoco, Donald E. Steiss, Jonathan Elliot Bergsagel, Jason A.T. Jones
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Publication number: 20210165744Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.Type: ApplicationFiled: February 9, 2021Publication date: June 3, 2021Inventors: Sriramakrishnan GOVINDARAJAN, Gregory Raymond SHURTZ, Mihir Narendra MODY, Charles Lance FUOCO, Donald E. STEISS, Jonathan Elliot BERGSAGEL, Jason A.T. JONES
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Patent number: 10949357Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.Type: GrantFiled: January 24, 2019Date of Patent: March 16, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sriramakrishnan Govindarajan, Gregory Raymond Shurtz, Mihir Narendra Mody, Charles Lance Fuoco, Donald E. Steiss, Jonathan Elliot Bergsagel, Jason A. T. Jones
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Publication number: 20200242048Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.Type: ApplicationFiled: January 24, 2019Publication date: July 30, 2020Inventors: Sriramakrishnan GOVINDARAJAN, Gregory Raymond SHURTZ, Mihir Narendra MODY, Charles Lance FUOCO, Donald E. STEISS, Jonathan Elliot BERGSAGEL, Jason A.T. JONES
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Patent number: 10540736Abstract: An integrated circuit includes a display sub-system that has a plurality of image processing resources and control logic. The image processing resources include a plurality of image processing pipelines configured to operate in parallel, overlay logic coupled to receive image data from the plurality of image processing pipelines, and an image output port coupled to an output of the overlay logic with image data outputs configured to couple to one or more display devices. The control logic is dynamically configurable to assign each of the image processing resources to a selected one of a first control port and a second control port. The first control port is configured to be controlled exclusively by a first processor and the second control port is configured to be controlled exclusively by a second processor.Type: GrantFiled: August 3, 2017Date of Patent: January 21, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sunita Nadampalli, Anish Reghunath, Brian Okchon Chae, Jonathan Elliot Bergsagel, Gregory Raymond Shurtz
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Patent number: 10395541Abstract: An integrated fault-tolerant augmented area viewing system includes, for example, a subsystem processor for receiving a safety signal for blind spot monitoring from a blind spot sensor and for generating a subsystem processor video output signal in response to the received safety signal. Selector circuitry selects the subsystem processor video output signal or a master controller video output signal received from a master controller and generates a selected video output signal in response. The selector circuitry performs the selection of the video output signal selection in response to receiving a safety request signal generated in response to a user action. A buffer outputs the selected video output signal for displaying on a display for viewing by the user.Type: GrantFiled: October 2, 2015Date of Patent: August 27, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jonathan Elliot Bergsagel, Sunita Nadampalli, Thomas Ray Shelburne, Aishwarya Dubey, Ian Carl Byers
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Publication number: 20190043153Abstract: An integrated circuit includes a display sub-system that has a plurality of image processing resources and control logic. The image processing resources include a plurality of image processing pipelines configured to operate in parallel, overlay logic coupled to receive image data from the plurality of image processing pipelines, and an image output port coupled to an output of the overlay logic with image data outputs configured to couple to one or more display devices. The control logic is dynamically configurable to assign each of the image processing resources to a selected one of a first control port and a second control port. The first control port is configured to be controlled exclusively by a first processor and the second control port is configured to be controlled exclusively by a second processor.Type: ApplicationFiled: August 3, 2017Publication date: February 7, 2019Inventors: Sunita Nadampalli, Anish Reghunath, Brian Okchon Chae, Jonathan Elliot Bergsagel, Gregory Raymond Shurtz
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Publication number: 20160210861Abstract: An integrated fault-tolerant augmented area viewing system includes, for example, a subsystem processor for receiving a safety signal for blind spot monitoring from a blind spot sensor and for generating a subsystem processor video output signal in response to the received safety signal. Selector circuitry selects the subsystem processor video output signal or a master controller video output signal received from a master controller and generates a selected video output signal in response. The selector circuitry performs the selection of the video output signal selection in response to receiving a safety request signal generated in response to a user action. A buffer outputs the selected video output signal for displaying on a display for viewing by the user.Type: ApplicationFiled: October 2, 2015Publication date: July 21, 2016Applicant: Texas Instruments IncorporatedInventors: Jonathan Elliot Bergsagel, Sunita Nadampalli, Thomas Ray Shelburne, Aishwarya Dubey, Ian Carl Byers