Patents by Inventor Jonathan ENOCH

Jonathan ENOCH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Variable precision floating point multiply-add circuit
    Patent number: 9104474
    Abstract: Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Ram K. Krishnamurthy, William C. Hasenplaugh, Randy L. Allmon, Jonathan Enoch
  • VARIABLE PRECISION FLOATING POINT MULTIPLY-ADD CIRCUIT
    Publication number: 20140188968
    Abstract: Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Himanshu KAUL, Mark A. ANDERS, Sanu K. MATHEW, Ram K. KRISHNAMURTHY, William C. HASENPLAUGH, Randy L. ALLMON, Jonathan ENOCH