Abstract: A power line communication device comprises a plurality of transformers in series. These transformers are used to increase the voltage of a digitally encoded signal in a stepwise fashion prior to being coupled into a power line. While a transmit path includes at least a first transformer and a second transformer in series, a receive path may include only one of these two transformers. For example a receive path may include only the first transformer, or include the first transformer and a third transformer. The net ratio of voltage increase and decrease may be different in the transmit and receive paths.

Abstract: A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Abstract: An imaging assembly for an image sensor may include a lens, a transparent substrate and two aspherical optical coatings on each side of the substrate. The imaging assembly can also incorporate an opaque coating with an opening in-line with the lens to form an aperture, an anti-reflection coating, and an infrared filter coating.

Abstract: An image sensor includes an array of pixels, with each pixel including a photodiode, and a first output circuit for deriving a linear output signal by applying a reset signal to the photodiode and reading a voltage on the photodiode after an integration time. A second output circuit derives a logarithmic output signal by reading a near instantaneous illumination-dependent voltage on the photodiode that is a logarithmic function of the illumination. In the logarithmic mode, the pixels are calibrated to remove fixed pattern noise. The pixels may be operated in linear and log modes sequentially, with the linear output being selected for low light signals and the log output being selected for high light signals.

Abstract: A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Abstract: A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Abstract: A power line communication device comprises a plurality of transformers in series. These transformers are used to increase the voltage of a digitally encoded signal in a stepwise fashion prior to being coupled into a power line. While a transmit path includes at least a first transformer and a second transformer in series, a receive path may include only one of these two transformers. For example a receive path may include only the first transformer, or include the first transformer and a third transformer. The net ratio of voltage increase and decrease may be different in the transmit and receive paths.

Abstract: A resistor-input transconductor includes a circuit configured to generate a common-mode compensation current. The common-mode compensation current is used to compensate for the common-mode voltage of the inputs. A current output of the resistor-input transconductor is proportional to a voltage difference between the two inputs and essentially independent of a common-mode voltage of the two inputs. The resistor input transconductor may be applied in a variety of applications including, for example, communications.

Abstract: An image plane includes a plurality of pixels. Each pixel comprises a photodiode and two transistors, and each pixel is connected by a signal bus to a respective storage node located off the image plane. Each storage node comprises two capacitors and associated switches. One of the transistors applies a reset pulse to the pixel, and the other transistor connects the pixel to a given conductor of the signal bus, which is then connected to the storage node. The pixel transistors can be operated simultaneously, and the sensed values can subsequently be transferred from the storage nodes sequentially.

Abstract: An image sensor has an array of pixels read by column circuits to provide reset and read samples on a pair of sample capacitors. To alleviate the effects of parasitic capacitance in the region of the sample capacitors, a modified timing arrangement is used. Both sample switches are operated simultaneously to pre-charge both sample capacitors with a pixel signal value. One sample switch is operated after reset to apply a reset value to one of the pre-charged sample capacitors.

Abstract: A method of operating a solid state image sensor (1) for the acquisition of an image generated by an asynchronous stimulus (S) is described in which the sensor is operated in conjunction with at least one detector (4) which detects the said asynchronous stimulus. The sensor is regularly reset so as to commence integration from a reset state of the sensor each time a period Tr has elapsed. The output of the detector(s) prior to each reset (R) is used to determine whether that reset is inhibited or not, whereby the likelihood of the stimulus being corrupted is prevented, or at least substantially reduced. A method is also proposed in which a portion of the sensor array is itself used as the detector (4) for detecting the asynchronous stimulus. A solid state image sensor incorporating a reset inhibition control function for carrying out the described method is also claimed.

Abstract: Lighting flicker in the output of a video imaging device is detected. The video imaging device has a main picture area divided into pixels for producing successive images at a frame rate. A series of signals are produced from at least one additional picture area adjacent the main picture area, with the additional picture area having a size substantially larger than a pixel. Each of the signals is a function of light incident on the additional picture area in a time period substantially shorter than that of the frame rate. A predetermined number of the signals are accumulated to form a series of compound samples, and the compound samples are filtered to detect components indicating the lighting flicker. The filtering is performed using a bandpass filter tuned to the nominal flicker frequency. The compound samples are formed at a sample rate which is a multiple of the nominal flicker frequency, and the filtering is performed by taking the fundamental output component of a radix-N butterfly.

Abstract: Solid state image sensors, and methods of operation thereof, includes an array of photosensitive pixels arranged in rows and columns and in which pixel data signals are read out from the pixels via column circuits, which introduces column fixed pattern noise to the signals. The signals are selectively inverted at the inputs to the column circuits and the inversion is reversed following output from the column circuits. Each column circuit may include an analog-to-digital converter and a digital inverter for inverting digital output therefrom. The selective inversion may be applied to alternate rows or groups of rows of the pixel data, and may be applied differently to different frames of the pixel data. These techniques result in column fixed pattern noise being modulated in a manner which makes the noise less apparent to the eye, and which facilitates subsequent cancellation of the noise.

Abstract: An image sensor includes an array of pixels, with each pixel including a photodiode, and a first output circuit for deriving a linear output signal by applying a reset signal to the photodiode and reading a voltage on the photodiode after an integration time. A second output circuit derives a logarithmic output signal by reading a near instantaneous illumination-dependent voltage on the photodiode that is a logarithmic function of the illumination. In the logarithmic mode, the pixels are calibrated to remove fixed pattern noise. The pixels may be operated in linear and log modes sequentially, with the linear output being selected for low light signals and the log output being selected for high light signals.

Abstract: A logarithmic pixel is formed by a photodiode connected to a semiconductor device that is operating based upon a sub-threshold. A logarithmic output is taken from an output node connected to the pixel via an amplifier. To calibrate the pixel, the photodiode is isolated by a switch and a ramp voltage is applied as reference voltage to the amplifier. The ramp voltage acts across the constant internal capacitance of the pixel to produce in-pixel a constant current for calibration purposes.

Abstract: An active pixel array has the signal output of each pixel connected to a first column conductor, and a reset switch connected to a second column conductor. The first and second column conductors are connected to a read-reset amplifier. The read-reset amplifier operates in a first mode in which a reset voltage is applied to the second column line, and in a second mode in which pixel output signals are buffered from the first column line. The read-reset amplifier can also operate as a comparator forming part of an ADC circuit.

Abstract: An image sensor has an array of pixels read by column circuits to provide reset and read samples on a pair of sample capacitors. To alleviate the effects of parasitic capacitance in the region of the sample capacitors, a modified timing arrangement is used. Both sample switches are operated simultaneously to pre-charge both sample capacitors with a pixel signal value. One sample switch is operated after reset to apply a reset value to one of the pre-charged sample capacitors.

Abstract: A solid state image sensor may include a pixel array of an active pixel type including three transistors and a photodiode for each pixel. Pixel reset values may be read out one row at a time and stored in a frame store. Pixel signal values may also be read out a row at a time. The stored reset values may be subtracted, for example, by a read/write/modify circuit to remove kTC noise. The readout of the reset and signal values may be interleaved, and the offset between read and reset for each row may be selected to control frame exposure.

Abstract: An active pixel array has the signal output of each pixel connected to a first column conductor, and a reset switch connected to a second column conductor. The first and second column conductors are connected to a read-reset amplifier. The read-reset amplifier operates in a first mode in which a reset voltage is applied to the second column line, and in a second mode in which pixel output signals are buffered from the first column line. The read-reset amplifier can also operate as a comparator forming part of an ADC circuit.

Abstract: An integrated circuit suitable for use as a multi-spectral image array sensor (1) comprises an array of pixels (2) for sensing radiation of different wavelengths e.g. different colours. The array has at least one row of cells containing a plurality of series (R,G) of pixels which series are interspersed with each other. Each series consists essentially of pixels (2) for sensing radiation of substantially the same wavelength e.g. the same colour. At least two horizontal shift registers (16,18) are provided, each register being coupled to pixels (2) of a respective one of the plurality of series (R,G) of pixels so as to enable the outputs from the pixels of each series to be read out consecutively at an array output (11). In a preferred embodiment the pixels (2) are preferably arranged in a Bayer matrix of Red, Green and Blue pixels and two interleaved shift registers (16,18) are provided for reading out the pixel outputs for each colour consecutively, in each row.