Patents by Inventor Jonathan Ferro

Jonathan Ferro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit chip design
    Patent number: 7243323
    Abstract: Method of developing a model of a circuit design including the steps of generating four different path-tracing runs, creating four arcs from the four different path-tracing runs, and combining the four arcs into two separate models. Also, a method of adjusting timing of a clock signal provided to a first block and a second block where data signals travel via a first path from the first block to the second block and data signals travel via a second path from the second block to the first block and the time for the data signals to travel the first path is greater than the time for the data signals to travel the second path. The clock signal provided to the second block relative to the clock signal provided to the first block is delayed by an amount that is a function of the difference between the time for the data signals to travel the first path and the time for the data signals to travel the second path.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: July 10, 2007
    Assignee: Infineon Technologies AG
    Inventors: Ted E. Williams, Jonathan Ferro, DeForest Tovey, Louis Tseng
  • Integrated circuit chip design
    Publication number: 20030051222
    Abstract: Methods are disclosed for improving the design of integrated circuits.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 13, 2003
    Inventors: Ted E. Williams, Jonathan Ferro, DeForest Tovey, Louis Tseng