Abstract: Examples provide an accessibility manager enabling a persistent floating secondary stage for presentation of user-configurable content during a video conferencing meeting. A primary stage is provided during each video conferencing meeting. The primary stage includes a roster of meeting attendees and an area for displaying shared content. The user creates configurable settings which are used at every meeting to generate a customized secondary stage. The secondary stage is an overlay which persists on the user interface even if the primary stage is minimized as the user multi-tasks during the meeting. The secondary stage displays video feed for one or more selected meeting attendees, such as an interpreter. When an interpreter speaks on behalf of the user, the user receives the active speaker attribution. The configurable settings permit the user to control the secondary stage video feed quality, sizing, aspect ratio, display location, captioning, role designation and active speaker designation.

Abstract: Examples provide an accessibility manager enabling a persistent floating secondary stage for presentation of user-configurable content during a video conferencing meeting. A primary stage is provided during each video conferencing meeting. The primary stage includes a roster of meeting attendees and an area for displaying shared content. The user creates configurable settings which are used at every meeting to generate a customized secondary stage. The secondary stage is an overlay which persists on the user interface even if the primary stage is minimized as the user multi-tasks during the meeting. The secondary stage displays video feed for one or more selected meeting attendees, such as an interpreter. When an interpreter speaks on behalf of the user, the user receives the active speaker attribution. The configurable settings permit the user to control the secondary stage video feed quality, sizing, aspect ratio, display location, captioning, role designation and active speaker designation.

Abstract: A mechanism to raise and lower the sail of a boat includes a headcar movably secured to a mast of the boat and a headboard affixed to the sail. A pulling force applied to a halyard raises the sail and causes the headboard to engage the headcar. When the sail is lowered, the headboard disengages from the headcar so that the sail furls flat on the boom.

Abstract: A mechanism to raise and lower the sail of a boat includes a headcar movably secured to a mast of the boat and a headboard affixed to the sail. A pulling force applied to a halyard raises the sail and causes the headboard to engage the headcar. When the sail is lowered, the headboard disengages from the headcar so that the sail furls flat on the boom.

Abstract: The present invention is directed to plants that display a drought tolerance phenotype due to altered expression of a DR02 nucleic acid. The invention is further directed to methods of generating plants with a drought tolerance phenotype.

Abstract: The present invention is directed to plants that display a pathogen resistance phenotype due to altered expression of a PPR2 nucleic acid. The invention is further directed to methods of generating plants with a pathogen resistance phenotype.

Abstract: A sampling system includes an input terminal for receiving a data signal having a signal component and possibly a noise component. A sampler samples the data signal at a sample rate set in responsive to a control signal. A noise detector detects the presence of a noise component, and if a noise component is detected, generates the control signal conditioning the sampler to sample the data signal at a first sample rate satisfying the Nyquist criterion for the data signal including the noise component, and otherwise generating the control signal conditioning the sampler to sample the data signal at a second data rate satisfying the Nyquist criterion for the data signal including only the signal component.

Abstract: A sampling system includes an input terminal for receiving a data signal having a signal component and possibly a noise component. A sampler samples the data signal at a sample rate set in responsive to a control signal. A noise detector detects the presence of a noise component, and if a noise component is detected, generates the control signal conditioning the sampler to sample the data signal at a first sample rate satisfying the Nyquist criterion for the data signal including the noise component, and otherwise generating the control signal conditioning the sampler to sample the data signal at a second data rate satisfying the Nyquist criterion for the data signal including only the signal component.

Abstract: Internet-based enhanced radio. The radio appliance, through a network interface and Internet service provider, accesses a tuning service built upon a plurality of databases. The tuning service, databases, and related enhanced services provide the listener a variety of services, complimenting AM/FM radio broadcasts and Internet radio media stream broadcasts. The radio appliance user can request additional information concerning advertised products, identify and purchase soundtracks and CDs, purchase advertised products, and respond to market research polling and surveys. The tuning service and related enhanced services can monitor, collect, process, and store user music preferences, polling and survey results, user behavior statistics, and purchase and information requests. Market research and subscriber information is stored, retrieved, and updated in databases accessible to the tuning service.

Abstract: An address selective address mapping system comprises an address translation circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The address translation circuit's inputs are coupled to the first address bus, and the address translation circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the address translation circuit. The address translation circuit determines whether the pointer address indicates that the next source instruction is within the subset of the most frequently executed source instructions. If so, the address translation circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the address translation circuit unchanged.

Abstract: An apparatus and method for emulation routine pointer prefetch are disclosed. The apparatus includes an emulated program counter (EPC), a prefetch state machine, a summing device, an opcode storage device, and a pointer storage device. The EPC, opcode storage device and pointer storage device are coupled to a bus to receive, store and output an emulated program counter value, an opcode value and a pointer to a next emulation routine. The EPC, opcode storage device, and pointer storage device are controlled by the prefetch state machine, which also is coupled to the bus to detect a reference to a reserved memory address and stores an updated emulated program counter value in the EPC using the summing device. The prefetch state machine uses the EPC value to prefetch the next source instruction to be emulated in a first memory operation. A portion of the prefetched source instruction is the opcode value and is stored in the opcode storage device.

Abstract: An apparatus for emulation routine control transfer creates a jump host instruction (JHI) containing the address of a next emulation routine during the execution of a current emulation routine and outputs the JHI at the end of current emulation routine for transfer of host processor control. The apparatus preferably comprises: an emulated program counter (EPC), a summing means, a state machine, a pointer storage means, an opcode storage means, and a jump instruction circuit. The state machine is preferably coupled to control the loading of the EPC, the loading of the opcode storage means, the summing means, the pointer storage means and the operation of the jump instruction circuit. The pointer storage means is preferably coupled between the data bus and the jump instruction circuit.

Abstract: An instruction mapping system comprises an instruction mapping circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The instruction mapping circuit's address inputs are coupled to the first address bus, and the instruction mapping circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the instruction mapping circuit. The instruction mapping circuit determines whether the pointer address indicates that the next source instruction is within the subset of most frequently executed source instructions. If so, the instruction mapping circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the instruction mapping circuit unchanged.

Abstract: An apparatus for emulation routine instruction issue comprises a bus signal router, a state machine, a virtual program counter (VPC) circuit, an emulated program counter (EPC), a summing circuit, an opcode storage register, and a pointer storage register. The VPC circuit maintains the VPC value under the direction of the state machine. In response to a next instruction request issued by the central processing unit (CPU), the state machine outputs the VPC to an instruction address bus, transferring the host instruction stored at the address indicated by the VPC to the instruction bus for issue to the CPU. After a next host instruction request, the state machine updates the VPC value. Concurrent with the execution of the current emulation routine, the state machine prefetches the nest emulation routine pointer (NERP) by issuing DMA commands and commands to the EPC, the opcode storage means, and the pointer storage means.

Abstract: A printed circuit board card adapted to fit into a slot and make electrical connections with cooperating terminals in the slot, the slot being disposed on the main circuit board of a personal computer system, the main circuit board including a CPU, memory, a 32-bit address bus with control signals associated therewith, and input/output circuity. The slot is coupled to the 32-bit address bus, being substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The card includes a decoder means which is coupled to the slot to receive the identification number; the decoder means has memory reservation means which causes 256 megabytes of memory space to be reserved for the card in the slot, such that, where the slot number is X, the 256 megabytes of reserved memory space begins at location $X000 0000 and ends at location $XFFF FFFF.

Abstract: A personal computer system includes a main circuit board having a central processing unit and expansion slots each of which is adapted to receive a printed circuit board card. The main circuit board further includes memory, a 32-bit address bus with control signals associated therewith, and input/output circuitry. The slot is coupled to the 32-bit address bus, which is substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The computer system reserves 256-megabytes of memory space ranging from location $X000 0000 to location $XFFF FFFF for memory on a card in a slot having a distinct number equal to $X.