Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive at least first and second different Data-Flow Graphs (DFGs), each specifying code instructions, and to configure at least some of the compute nodes and interconnects in the compute fabric to concurrently execute the code instructions specified in the first and second DFGs, and send to the compute fabric multiple first threads that execute the code instructions specified in the first DFG and multiple second threads that execute the code instructions specified in the second DFG, thereby causing the compute fabric to execute, at least during a given time interval, both code instructions specified in the first DFG and code instructions specified in the second DFG.

Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive at least first and second different Data-Flow Graphs (DFGs), each specifying code instructions, and to configure at least some of the compute nodes and interconnects in the compute fabric to concurrently execute the code instructions specified in the first and second DFGs, and send to the compute fabric multiple first threads that execute the code instructions specified in the first DFG and multiple second threads that execute the code instructions specified in the second DFG, thereby causing the compute fabric to execute, at least during a given time interval, both code instructions specified in the first DFG and code instructions specified in the second DFG.

Abstract: There is disclosed a method and device for operating an image database shared by a plurality of users. In an embodiment, each image captured by a user and stored in a shared image database is associating with the geographic coordinates of the location at which the image was captured. A search engine for the image database is configured to accept geographic coordinates as a search criterion for locating at least one captured image stored in the shared image database. The images having location coordinates within a predefined range of geographic coordinates is displayed to the user.

Abstract: An advanced split microwave architecture is provided. The advanced split microwave architecture includes a smart outdoor communication unit including a digital N-Plexer configured to multiplex and/or demultiplex a received data signal in the digital domain, a processor unit configured to carry out instructions to control operation of the digital N-Plexer, and a converter module configured to convert the received data signal between the digital domain and the analog domain. The smart outdoor communication unit further includes an RF module, having digital capabilities, configured to correct errors within the received data signal in the digital domain, perform a conversion of the received data signal, to amplify a power of the received data signal, and to perform automatic gain control in the digital domain.

Abstract: There is disclosed a method and device for operating an image database shared by a plurality of users. In an embodiment, each image captured by a user and stored in a shared image database is associating with the geographic coordinates of the location at which the image was captured. A search engine for the image database is configured to accept geographic coordinates as a search criterion for locating at least one captured image stored in the shared image database. The images having location coordinates within a predefined range of geographic coordinates is displayed to the user.

Abstract: A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions in a first segment of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions in a second segment of the instructions, at least partially in parallel with processing of the instructions of the first segment by the first hardware thread, in accordance with a specification of register access that is indicative of data dependencies between the first and second segments.

Abstract: A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions at least partially in parallel with processing of the instructions by the first hardware thread.

Abstract: There is disclosed a method and device for operating an image database shared by a plurality of users. In an embodiment, each image captured by a user and stored in a shared image database is associating with the geographic coordinates of the location at which the image was captured. A search engine for the image database is configured to accept geographic coordinates as a search criterion for locating at least one captured image stored in the shared image database. The images having location coordinates within a predefined range of geographic coordinates is displayed to the user.

Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. A relationship between the memory addresses accessed by two or more of the memory-access instructions is identified, based on respective formats of the memory addresses specified in the symbolic expressions. An outcome of at least one of the memory-access instructions is assigned to be served from an internal memory in the processor, based on the identified relationship.

Abstract: A processor includes a processing pipeline including multiple hardware threads and configured to execute software code instructions that are stored in a memory, along with multiple registers, configured to be read and written to by the processing pipeline during execution of the instructions. A monitoring unit monitors the instructions in the processing pipeline and records respective monitoring tables indicating the registers accessed in processing the instructions in different sequences of the instructions, and parallelizes among the hardware threads of the processor, using the respective monitoring tables, execution of repetitions of at least first sequences of the instructions.

Abstract: A communications network is disclosed that includes one or more microwave backhaul nodes for routing communications between one or more near end mobile communications devices and one or more far end mobile communications devices. The communications network includes a central monitoring and control infrastructure, a remote monitoring and control infrastructure and/or a local monitoring and control infrastructure. The central monitoring and control infrastructure, the remote monitoring and control infrastructure and/or the local monitoring and control infrastructure can directly manage the one or more microwave backhaul nodes. Alternatively, the remote monitoring and control infrastructure and/or the local monitoring and control infrastructure can indirectly manage the one or more microwave backhaul nodes through the central monitoring and control infrastructure.

Abstract: A communications network is disclosed that includes one or more microwave backhaul nodes for routing communications between one or more near end mobile communications devices and one or more far end mobile communications devices. The communications network includes a central monitoring and control infrastructure, a remote monitoring and control infrastructure and/or a local monitoring and control infrastructure. The central monitoring and control infrastructure, the remote monitoring and control infrastructure and/or the local monitoring and control infrastructure can directly manage the one or more microwave backhaul nodes. Alternatively, the remote monitoring and control infrastructure and/or the local monitoring and control infrastructure can indirectly manage the one or more microwave backhaul nodes through the central monitoring and control infrastructure.

Abstract: A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.

Abstract: A method includes, in a processor (20) that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.

Abstract: Method(s) for up/down fusion and/or pseudo-fusion of micro-operations are performed in a hardware processor configured to execute program code. A mergeable pair of micro-operations is identified in a sequence of micro-operations of the program code. The pair of micro-operations includes a first micro-operation for performing a first function and a non-consecutive second micro-operation for performing a second function. The first micro-operation precedes the second micro-operation in the sequence of micro-operations being processed. The first micro-operation is merged into the second micro-operation to create a third micro-operation which performs both the first function and the second function. In up/down fusion the third micro-operation is dispatched instead of the first micro-operation or instead of the second micro-operation, based on whether fuse-up or fuse-down is performed.

Abstract: Method(s) for up/down fusion and/or pseudo-fusion of micro-operations are performed in a hardware processor configured to execute program code. A mergeable pair of micro-operations is identified in a sequence of micro-operations of the program code. The pair of micro-operations includes a first micro-operation for performing a first function and a non-consecutive second micro-operation for performing a second function. The first micro-operation precedes the second micro-operation in the sequence of micro-operations being processed. The first micro-operation is merged into the second micro-operation to create a third micro-operation which performs both the first function and the second function. In up/down fusion the third micro-operation is dispatched instead of the first micro-operation or instead of the second micro-operation, based on whether fuse-up or fuse-down is performed.

Abstract: A method includes retrieving to a pipeline of a processor first instructions of program code from a first region in the program code. Before fully determining a flow-control path, which is to be traversed within the first region until exit from the first region, a beginning of a second region in the code that is to be processed following the first region is predicted, and second instructions begin to be retrieved to the pipeline from the second region. The retrieved first instructions and second instructions are processed by the pipeline.

Abstract: A method includes, in a processor having a pipeline, fetching instructions of program code at run-time, in an order that is different from an order-of-appearance of the instructions in the program code. The instructions are divided into segments having segment identifiers (IDs). An event, which warrants flushing of instructions starting from an instruction belonging to a segment, is detected. In response to the event, at least some of the instructions in the segment that are subsequent to the instruction, and at least some of the instructions in one or more subsequent segments that are subsequent to the segment, are flushed from the pipeline based on the segment IDs.

Abstract: A communications network is disclosed that includes one or more microwave backhaul nodes for routing communications between one or more near end mobile communications devices and one or more far end mobile communications devices. The communications network includes a central monitoring and control infrastructure, a remote monitoring and control infrastructure and/or a local monitoring and control infrastructure. The central monitoring and control infrastructure, the remote monitoring and control infrastructure and/or the local monitoring and control infrastructure can directly manage the one or more microwave backhaul nodes. Alternatively, the remote monitoring and control infrastructure and/or the local monitoring and control infrastructure can indirectly manage the one or more microwave backhaul nodes through the central monitoring and control infrastructure.

Abstract: A processor includes an instruction pipeline and control circuitry. The instruction pipeline is configured to process instructions of program code. The control circuitry is configured to monitor the processed instructions at run-time, to construct an invocation data structure comprising multiple entries, wherein each entry (i) specifies an initial instruction that is a target of a branch instruction, (ii) specifies a portion of the program code that follows one or more possible flow-control traces beginning from the initial instruction, and (iii) specifies, for each possible flow-control trace specified in the entry, a next entry that is to be processed following processing of that possible flow-control trace, and to configure the instruction pipeline to process segments of the program code, by continually traversing the entries of the invocation data structure.