Patents by Inventor Jonathan G. Bornstein

Jonathan G. Bornstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6709882
    Abstract: A method for making a resistive heater for a planar lightwave circuit. The method includes the step of depositing a resistive layer on a top clad of a planar lightwave circuit. An interconnect layer is subsequently deposited over the resistive layer. The resistive layer can be tungsten and the interconnect layer can be aluminum. The interconnect layer is then etched to define a heater interconnect, wherein the heater interconnect is disposed over the resistive layer and has a first width. The heater interconnect is then masked, and the resistive layer is etched to define a resistive heater. The resistive heater is disposed beneath the heater interconnect and has a second width larger than the first width.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: March 23, 2004
    Assignee: Lightwave Microsystems Corporation
    Inventors: Pamela S. Trammel, Jonathan G. Bornstein, David H. Menche
  • Patent number: 6705124
    Abstract: A method for performing high aspect ratio gap fill during planar lightwave circuit top clad deposition. A plurality of waveguide cores are formed on a substrate, the waveguide cores having a plurality of gaps there between. A cladding layer is formed over the waveguide cores and the substrate using a high-density plasma deposition process. The refractive index of the waveguide cores are controlled by using a dopant to be higher than the refractive of the cladding layer. An anneal process is performed on the cladding layer after the high-density plasma deposition process. The gaps between the waveguide cores can be smaller than 2 microns. The aspect ratio of the gaps between the waveguide cores can be greater than 3. The high-density plasma deposition process provides a very high purity USG (undoped silica glass) and BPSG (Boron Phosphorous silica glass) layers having a uniform refractive index.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: March 16, 2004
    Assignee: Lightwave Microsystems Corporation
    Inventors: Fan Zhong, Jonathan G. Bornstein
  • Patent number: 6615615
    Abstract: A method of depositing a core layer for an optical waveguide structure of a planar lightwave circuit. A GePSG core for an optical waveguide structure of a planar lightwave circuit is fabricated such that the optical core comprises doped silica glass, wherein the dopant includes Ge and P. In depositing a core layer from which the optical core is formed, two separate doping gasses (e.g., GeH4 and PH3) are added during the PECVD process to make Ge and P doped silica glass (GePSG). The ratio of the Ge dopant and the P dopant is configured to maintain a constant refractive index within the core layer across an anneal temperature range and to reduce a formation of bubbles within the core layer. The ratio of the Ge dopant and the P dopant is also configured to reduce refractive index birefringence within the core layer across an anneal temperature range.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 9, 2003
    Assignee: Lightwave Microsystems Corporation
    Inventors: Fan Zhong, Jonathan G. Bornstein
  • Publication number: 20030040135
    Abstract: A method for making a resistive heater for a planar lightwave circuit. The method includes the step of depositing a resistive layer on a top clad of a planar lightwave circuit. An interconnect layer is subsequently deposited over the resistive layer. The resistive layer can be tungsten and the interconnect layer can be aluminum. The interconnect layer is then etched to define a heater interconnect, wherein the heater interconnect is disposed over the resistive layer and has a first width. The heater interconnect is then masked, and the resistive layer is etched to define a resistive heater. The resistive heater is disposed beneath the heater interconnect and has a second width larger than the first width.
    Type: Application
    Filed: August 27, 2001
    Publication date: February 27, 2003
    Inventors: Pamela S. Trammel, Jonathan G. Bornstein, David H. Menche
  • Publication number: 20030002836
    Abstract: A method of depositing a core layer for an optical waveguide structure of a planar lightwave circuit. A GePSG core for an optical waveguide structure of a planar lightwave circuit is fabricated such that the optical core comprises doped silica glass, wherein the dopant includes Ge and P. In depositing a core layer from which the optical core is formed, two separate doping gasses (e.g., GeH4 and PH3) are added during the PECVD process to make Ge and P doped silica glass (GePSG). The ratio of the Ge dopant and the P dopant is configured to maintain a constant refractive index within the core layer across an anneal temperature range and to reduce a formation of bubbles within the core layer. The ratio of the Ge dopant and the P dopant is also configured to reduce refractive index birefringence within the core layer across an anneal temperature range. A thermal anneal process for the core layer can be a temperature within a range of 900 C. to 1200 C.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Fan Zhong, Jonathan G. Bornstein
  • Publication number: 20030000918
    Abstract: In a planar lightwave circuit, a method of making an optical waveguide that resists core deformation. The method includes a step of forming a core layer on a bottom clad. A waveguide core is formed from the core layer using an etching process. The waveguide core is fabricated to have a higher refractive index than the bottom clad. A silica glass cap layer is then formed over the waveguide core and the bottom clad. A top clad is then formed over the waveguide core, the silica glass cap layer, and the bottom clad. The waveguide core has a higher refractive index than the top clad. The silica glass cap layer maintains the shape of the waveguide core during an anneal process of the top clad. The silica glass cap layer can be deposited using PECVD (plasma enhanced chemical vapor deposition). The silica glass cap layer can be between 0.3 to 2 microns thick. The silica glass cap layer can be undoped silica glass.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Nizar S. Kheraj, Pamela S. Trammel, Fan Zhong, Jonathan G. Bornstein
  • Publication number: 20020178759
    Abstract: A method for performing high aspect ratio gap fill during planar lightwave circuit top clad deposition. A plurality of waveguide cores are formed on a substrate, the waveguide cores having a plurality of gaps there between. A cladding layer is formed over the waveguide cores and the substrate using a high-density plasma deposition process. The refractive index of the waveguide cores are controlled by using a dopant to be higher than the refractive of the cladding layer. An anneal process is performed on the cladding layer after the high-density plasma deposition process. The gaps between the waveguide cores can be smaller than 2 microns. The aspect ratio of the gaps between the waveguide cores can be greater than 3. The high-density plasma deposition process provides a very high purity USG (undoped silica glass) and BPSG (Boron Phosphorous silica glass) layers having a uniform refractive index.
    Type: Application
    Filed: June 4, 2001
    Publication date: December 5, 2002
    Inventors: Fan Zhong, Jonathan G. Bornstein
  • Patent number: 5661592
    Abstract: A deformable grating aparatus for modulating light is made by forming an insulating layer on a substrate, forming a first conductive layer on the insulating layer and then forming a sacrificial layer thereon. The sacrificial layer and the first conducting layer are then etched to define bit lines and busses to bonding pads. Then a layer of resilient material is formed onto the etched layers and a reflective conducting layer is formed on the resilient layer. A dielectric layer is deposited on the reflective conducting layer. The dielectric layer, the reflective conducting layer, the resilient layer and the sacrificial layer are all then etched to form a grating including a plurality of parallel elements. Thereafter the sacrificial layer is removed below the parallel elements, to suspend the parallel elements over the first conducting layer. The surface is treated to prevent the grating from adhering to the first conducting layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 26, 1997
    Assignee: Silicon Light Machines
    Inventors: Jonathan G. Bornstein, William C. Banyai, David M. Bloom, Ralph G. Whitten, Bryan P. Staker
  • Patent number: 4876117
    Abstract: Hard magnetic recording disks include a rigid substrate, typically aluminum, ceramic, or glass, having an underlayer thereover, typically being nickel-phosphorus. A ferromagnetic film is formed over the underlayer, and a protective coating layer formed over the ferromagnetic layer. The protective coating layer is a metal oxide formed by applying a liquid metal oxide precursor material over the ferromagnetic layer, and curing the liquid precursor material to leave a metal oxide layer in place. Optionally, a lubricating or carbon layer may be formed over the protective layer.
    Type: Grant
    Filed: February 4, 1988
    Date of Patent: October 24, 1989
    Assignee: Domain Technology
    Inventor: Jonathan G. Bornstein
  • Patent number: 4539625
    Abstract: A combined lighting system for a building interior includes a stack of luminescent solar concentrators (LSC), an optical conduit made of preferably optical fibers for transmitting daylight from the LSC stack, a collimating lens set at an angle, a fixture for receiving the daylight at one end and for distributing the daylight as illumination inside the building, an artificial light source at the other end of the fixture for directing artifical light into the fixture for distribution as illumination inside the building, an automatic dimmer/brightener for the artificial light source, and a daylight sensor positioned near to the LSC stack for controlling the automatic dimmer/brightener in response to the daylight sensed. The system also has a reflector positioned behind the artificial light source and a fan for exhausting heated air out of the fixture during summer and for forcing heated air into the fixture for passage into the building interior during winter.
    Type: Grant
    Filed: July 31, 1984
    Date of Patent: September 3, 1985
    Assignee: DHR, Incorporated
    Inventors: Jonathan G. Bornstein, Peter S. Friedman