Patents by Inventor Jonathan G. England

Jonathan G. England has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8937019
    Abstract: Techniques for forming a three dimensional (3D) feature on a substrate are disclosed. In one exemplary embodiment, the technique may be realized as a method comprising: forming a resist structure on the substrate, the resist structure having a first resist portion with a first thickness, a second resist portion with a second thickness, and a third resist portion with a third thickness, where the first thickness may be less than the second thickness, and where the second thickness may be less than the third thickness; implanting charged particles into the substrate through the first and second resist portions and forming an implanted region in the substrate; and etching the substrate to form the 3D feature on the substrate.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: January 20, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan G. England, Patrick M. Martin, David Cox
  • Publication number: 20130284697
    Abstract: Techniques for forming a three dimensional (3D) feature on a substrate are disclosed. In one exemplary embodiment, the technique may be realized as a method comprising: forming a resist structure on the substrate, the resist structure having a first resist portion with a first thickness, a second resist portion with a second thickness, and a third resist portion with a third thickness, where the first thickness may be less than the second thickness, and where the second thickness may be less than the third thickness; implanting charged particles into the substrate through the first and second resist portions and forming an implanted region in the substrate; and etching the substrate to form the 3D feature on the substrate.
    Type: Application
    Filed: April 2, 2013
    Publication date: October 31, 2013
    Inventors: Jonathan G. England, Patrick M. Martin, David Cox
  • Patent number: 8319196
    Abstract: A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter; a cooling mechanism within the pre-chill station configured to cool a wafer from ambient temperature to a predetermined range less than ambient temperature; a loading assembly coupled to the pre-chill station and the end station; and a controller in communication with the loading assembly and the cooling mechanism to coordinate loading a wafer into the pre-chill station, cooling the wafer down to the predetermined temperature range before any ion implantation into the wafer, and loading the cooled wafer into the end station where the cooled wafer undergoes an ion implantation process.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: November 27, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan G. England, Steven R. Walther, Richard S. Muka, Julian G. Blake, Paul J. Murphy, Reuel B. Liebert
  • Publication number: 20110207308
    Abstract: A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter; a cooling mechanism within the pre-chill station configured to cool a wafer from ambient temperature to a predetermined range less than ambient temperature; a loading assembly coupled to the pre-chill station and the end station; and a controller in communication with the loading assembly and the cooling mechanism to coordinate loading a wafer into the pre-chill station, cooling the wafer down to the predetermined temperature range before any ion implantation into the wafer, and loading the cooled wafer into the end station where the cooled wafer undergoes an ion implantation process.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 25, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Jonathan G. ENGLAND, Steven R. Walther, Richard S. Muka, Julian Blake, Paul J. Murphy, Reuel B. Liebert
  • Patent number: 8003498
    Abstract: Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: introducing a plurality of first particles to a first region of the substrate so as to form at least one crystal having a grain boundary in the first region without forming another crystal in a second region, the second region adjacent to the first region; and extending the grain boundary of the at least one crystal formed in the first region to the second region after stopping the introducing the plurality of first particles.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: August 23, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan G. England, Frank Sinclair, John (Bon-Woong) Koo, Rajesh Dorai, Ludovic Godet
  • Publication number: 20090124066
    Abstract: Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase.
    Type: Application
    Filed: November 12, 2008
    Publication date: May 14, 2009
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Jonathan G. ENGLAND, Frank Sinclair, John (Bon-Woong) Koo, Rajesh Dorai, Ludovic Godet
  • Publication number: 20090124065
    Abstract: Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase.
    Type: Application
    Filed: November 12, 2008
    Publication date: May 14, 2009
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Jonathan G. ENGLAND, Frank Sinclair, John (Bon-Woong) Koo, Rajesh Dorai, Ludovic Godet
  • Publication number: 20090124064
    Abstract: Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase.
    Type: Application
    Filed: November 12, 2008
    Publication date: May 14, 2009
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Jonathan G. ENGLAND, Rajesh Dorai, Ludovic Godet