Patents by Inventor Jonathan Glen Pfeifer

Jonathan Glen Pfeifer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9685932
    Abstract: Provided herein are apparatus and methods for enhancing bandwidth in trench isolated integrated circuits. In certain configurations, an auxiliary trench forming floating regions between moat isolation regions can isolate parasitic sidewall capacitances of active device regions from ground or AC ground. In this manner the active device regions are merged by the auxiliary trench so as to improve circuit bandwidth and enhance circuit performance. When arranged or combined within a circuit branch, transistors within each floating moat can operate with relatively small parasitic displacement current and can have improved performance.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: June 20, 2017
    Assignee: Analog Devices, Inc.
    Inventors: Edward P. Jordan, Jonathan Glen Pfeifer
  • Publication number: 20160336920
    Abstract: Provided herein are apparatus and methods for enhancing bandwidth in trench isolated integrated circuits. In certain configurations, an auxiliary trench forming floating regions between moat isolation regions can isolate parasitic sidewall capacitances of active device regions from ground or AC ground. In this manner the active device regions are merged by the auxiliary trench so as to improve circuit bandwidth and enhance circuit performance. When arranged or combined within a circuit branch, transistors within each floating moat can operate with relatively small parasitic displacement current and can have improved performance.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Edward P. Jordan, Jonathan Glen Pfeifer
  • Patent number: 9147677
    Abstract: Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: September 29, 2015
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Javier Alejandro Salcedo, David J Clarke, Jonathan Glen Pfeifer
  • Publication number: 20140339601
    Abstract: Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 20, 2014
    Applicant: Analog Devices Technology
    Inventors: Javier Alejandro Salcedo, David J. Clarke, Jonathan Glen Pfeifer
  • Publication number: 20040056333
    Abstract: An integrated circuit is divided into a number of sub-circuits by isolation walls in the substrate. A conducting shield overlays every sub-circuit to form a grounded cage with the underlying substrate for trapping electromagnetic radiation generated inside the sub-circuit, and to prevent cross-talk between the sub-circuits.
    Type: Application
    Filed: September 24, 2002
    Publication date: March 25, 2004
    Inventors: Hung Chang Lin, Sesha Rajamani Shankar, Jonathan Glen Pfeifer