Patents by Inventor Jonathan H. Griffith
Jonathan H. Griffith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10049909Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.Type: GrantFiled: February 14, 2017Date of Patent: August 14, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick, Edmund J. Sprogis
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Publication number: 20170154800Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.Type: ApplicationFiled: February 14, 2017Publication date: June 1, 2017Inventors: John J. Garant, Jonathan H. Griffith, Brittany L. HEDRICK, Edmund J. Sprogis
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Patent number: 9613842Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.Type: GrantFiled: February 19, 2014Date of Patent: April 4, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick, Edmund J. Sprogis
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Publication number: 20150235891Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick, Edmund J. Sprogis
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Patent number: 8807184Abstract: Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.Type: GrantFiled: February 22, 2013Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Sarah H. Knickerbocker, Jonathan H. Griffith
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Patent number: 8753460Abstract: Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.Type: GrantFiled: January 28, 2011Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Sarah H. Knickerbocker, Jonathan H. Griffith
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Patent number: 8314500Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.Type: GrantFiled: December 28, 2006Date of Patent: November 20, 2012Assignee: Ultratech, Inc.Inventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valérie Anne Oberson, Da-Yuan Shih, Kamalesh K Srivastava, Michael J. Sullivan
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Publication number: 20120193014Abstract: Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.Type: ApplicationFiled: January 28, 2011Publication date: August 2, 2012Applicant: International Business Machines CorporationInventors: SARAH H. KNICKERBOCKER, Jonathan H. Griffith
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Patent number: 7932169Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.Type: GrantFiled: October 5, 2009Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valérie Anne Oberson, Da-Yuan Shih, Kamalesh K Srivastava, Michael J. Sullivan
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Patent number: 7767575Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.Type: GrantFiled: January 2, 2009Date of Patent: August 3, 2010Assignee: Tessera Intellectual Properties, Inc.Inventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quinn, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Publication number: 20100062597Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.Type: ApplicationFiled: October 5, 2009Publication date: March 11, 2010Inventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valérie Anne Oberson, Da-Yuan Shih, Kamalesh K. Srivastava, Michael J. Sullivan
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Patent number: 7572726Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: GrantFiled: November 10, 2005Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Jonathan H. Griffith, Randolph F. Knarr, Sarah H. Knickerbocker, Kevin S. Petrarca, Roger A. Quon, Wolfgang Sauter, Kamalesh K. Srivastava, Richard P. Volant
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Publication number: 20090163019Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.Type: ApplicationFiled: January 2, 2009Publication date: June 25, 2009Applicant: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Patent number: 7473997Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: GrantFiled: September 12, 2005Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Publication number: 20080157395Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Inventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valerie Anne Oberson, Da-Yuan Shih, Kamalesh K. Srivastava, Michael J. Sullivan
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Patent number: 7144490Abstract: A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.Type: GrantFiled: November 18, 2003Date of Patent: December 5, 2006Assignee: International Business Machines CorporationInventors: Tien-Jen Cheng, David E. Eichstadt, Jonathan H. Griffith, Sarah H. Knickerbocker, Rosemary A. Previti-Kelly, Roger A. Quon, Kamalesh K. Srivastava, Keith Kwong-Hon Wong
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Patent number: 6995475Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: GrantFiled: September 18, 2003Date of Patent: February 7, 2006Assignee: International Business Machines CorporationInventors: Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Jonathan H. Griffith, Randolph F. Knarr, Sarah H. Knickerbocker, Kevin S. Petrarca, Roger A. Quon, Wolfgang Sauter, Kamalesh K. Srivastava, Richard P. Volant
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Patent number: 6995084Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: GrantFiled: March 17, 2004Date of Patent: February 7, 2006Assignee: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Patent number: 6992389Abstract: A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.Type: GrantFiled: April 28, 2004Date of Patent: January 31, 2006Assignee: International Business Machines CorporationInventors: Panayotis C. Andricacos, Tien-Jen J. Cheng, Emanuel I. Cooper, David E. Eichstadt, Jonathan H. Griffith, Randolph F. Knarr, Roger A. Quon, Erik J. Roggeman
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Patent number: 6531069Abstract: RIE processing chambers includes arrangements of gas outlets which force gas-flow-shadow elimination. Means are provided to control and adjust the direction of gases to the outlet to modify and control the direction of plasma flow at the wafer surface during processing. Means are provided to either move the exhaust paths for exhaust gases or to open and close exhaust paths sequentially, in a controlled manner, to modify flow directions of ions in the etching plasma. A combination of rotation/oscillation of a magnetic field imposed on the RIE chamber can be employed by rotation of permanent magnetic dipoles about the periphery of the RIE chamber or by controlling current through a coil wrapped around the periphery of the RIE process chamber to enhance the removal of the residues attributable to gas-flow-shadows formed by linear ion paths in the plasma.Type: GrantFiled: June 22, 2000Date of Patent: March 11, 2003Assignee: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Peter C. Wade, William H. Brearley, Jonathan H. Griffith