Abstract: Systems and methods for improving effective aging of a multi-core processor. Aging characteristics of the two or more cores of the multi-core processor are determined. Priority determination logic is configured to assign priorities for powering on the cores based on the aging characteristics. Optionally, an operating environment is detected and assigning priorities to the cores is based on a relative power consumption of each of the cores and the operating environment, in order to improve battery life.

Abstract: Embodiments of the invention include on-chip transistor degradation detection and compensation. In one embodiment of the invention, an integrated circuit is provided including a circuit with a body bias terminal coupled to a body of one or more transistors to receive a body bias voltage; a programmable degradation monitor to detect aging of transistors, and a body bias voltage generator coupled to the circuit and the programmable degradation monitor. The body bias voltage generator to adjust the body bias voltage coupled into the circuit in response to transistor aging detected by the programmable degradation monitor. The programmable degradation monitor includes a reference ring oscillator, an aged ring oscillator, and a comparison circuit. The comparison circuit to compare data delays in the reference ring oscillator and the aged ring oscillator to detect transistor aging within the integrated circuit.

Abstract: Provided are a method, system, and device to monitor degradation of a signal due to circuit aging. In one embodiment, a signal may be applied to a data path prior to aging of the circuit producing the signal to provide a reference value. The signal generating circuit may then be aged while the data path is disabled to protect the data path from the effects of circuit aging. Upon reenabling the data path, the signal may be reapplied in an after stress test to measure the effects of circuit aging on the circuitry generating the signal. For example, the effects of circuit aging may be measured for clock duty cycle degradation, clock skew degradation and signal margin degradation as well as other signal parameters. Additional embodiments are described and claimed.

Abstract: Embodiments of the invention include on-chip transistor degradation detection and compensation. In one embodiment of the invention, an integrated circuit is provided including a circuit with a body bias terminal coupled to a body of one or more transistors to receive a body bias voltage; a programmable degradation monitor to detect aging of transistors, and a body bias voltage generator coupled to the circuit and the programmable degradation monitor. The body bias voltage generator to adjust the body bias voltage coupled into the circuit in response to transistor aging detected by the programmable degradation monitor. The programmable degradation monitor includes a reference ring oscillator, an aged ring oscillator, and a comparison circuit. The comparison circuit to compare data delays in the reference ring oscillator and the aged ring oscillator to detect transistor aging within the integrated circuit.

Abstract: The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting the first clock signal using a variable delay device in response to the alignment offset signal to substantially align the edge of the first clock signal to the center of the data packet. Other embodiments are claimed and described.

Abstract: Embodiments of the invention include on-chip characterization of transistor degradation. In one embodiment, includes one or more functional blocks to perform one or more functions and an integrated on-chip characterization circuit to perform on-chip characterization of transistor degradation. The integrated on-chip characterization circuit includes a selectively enabled ring oscillator to generate a reference oscillating signal, a free-running ring oscillator to generate a free-running oscillating signal, and a comparison circuit coupled to the selectively enabled ring oscillator and the free-running ring oscillator. From the reference oscillating signal and the free-running oscillating signal, the comparison circuit determine a measure of transistor degradation.

Abstract: An embodiment of the present invention is a technique to monitor on-die device power grid. A sensor circuit generates a ground reference (GR) signal and N power reference (PR) signals forming a ladder according to a programmable configuration. The GR signal tracks a device ground signal of a device and the PR signals track a device power signal of the device. A comparator circuit compares the GR signal with the N PR signals to provide N comparison output signals, the N comparison output signals indicating position and time that the GR reference signal moves across the ladder.

Abstract: The present invention is related to method and apparatus for on-die noise detection that includes one more voltage noise sensors, and one or more associated comparators. The voltage noise sensor includes a circuit including devices designed to position an initial voltage level of nodes between the devices at certain levels. The nodes are paired where the initial level of one node is above the initial level of the other node in the pair. The devices are designed to position the initial voltage levels of nodes of each pair such that the occurrence of noise above a predefined threshold voltage causes at least one of the voltage levels at the pair of nodes to approach and pass the other. The comparator monitors the voltage levels of each pair of nodes and generates a trigger signal upon detection of the voltage levels at a pair of nodes passing each other.

Abstract: A method to calibrate I/O cell current has been described. The method includes setting a global control value provided to the I/O cells. Then, for each I/O cell, the method includes comparing the logic voltage at the output pad of the I/O cell with a reference voltage, and sinking more current at the output pad by enabling additional driver bits associated with the I/O cell if the logic voltage is higher than the reference voltage, or sinking less current at the output pad by disabling additional driver bits associated with the I/O cell if the logic voltage is lower than the reference voltage.

Abstract: An on-die noise detection circuit includes one or more voltage noise sensors, and one or more associated comparators. The voltage noise sensor includes a circuit including devices designed to position an initial voltage level of nodes between the devices at certain levels. The nodes are paired where the initial level of one node is above the initial level of the other node in the pair. The devices are designed to position the initial voltage levels of nodes of each pair such that the occurrence of noise above a predefined threshold voltage causes at least one of the voltage levels at the pair of nodes to approach and pass the other. The comparator monitors the voltage levels of each pair of nodes and generates a trigger signal upon detection of the voltage levels at a pair of nodes passing each other.

Abstract: A device on a source synchronous data bus includes a clock generation circuit which generates transmit and receive clock signals for transmitting and receiving data. The device sends data in quadrature phase relationship with the bus clock signal and receives data in phase with the bus clock signal.

Abstract: The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting the first clock signal using a variable delay device in response to the alignment offset signal to substantially align the edge of the first clock signal to the center of the data packet. Other embodiments are claimed and described.

Abstract: The present invention is related to method and apparatus for on-die noise detection that includes one more voltage noise sensors, and one or more associated comparators. The voltage noise sensor includes a circuit including devices designed to position an initial voltage level of nodes between the devices at certain levels. The nodes are paired where the initial level of one node is above the initial level of the other node in the pair. The devices are designed to position the initial voltage levels of nodes of each pair such that the occurrence of noise above a predefined threshold voltage causes at least one of the voltage levels at the pair of nodes to approach and pass the other. The comparator monitors the voltage levels of each pair of nodes and generates a trigger signal upon detection of the voltage levels at a pair of nodes passing each other.

Abstract: The invention includes a method to communicate a data packet. At a second input of a variable delay device, a first clock signal having at least one edge is received. At a first input of a detector, a first data packet having data that defines a second clock signal is received. At a second input of the detector, an output of the variable delay device is received. The output of the variable delay device is then compared to the second clock signal to produce an offset signal. The first clock signal is adjusted as a function of the offset signal to produce an output of the variable delay device.

Abstract: The present invention is related to method and apparatus for on-die noise detection that includes one more voltage noise sensors, and one or more associated comparators. The voltage noise sensor includes a circuit including devices designed to position an initial voltage level of nodes between the devices at certain levels. The nodes are paired where the initial level of one node is above the initial level of the other node in the pair. The devices are designed to position the initial voltage levels of nodes of each pair such that the occurrence of noise above a predefined threshold voltage causes at least one of the voltage levels at the pair of nodes to approach and pass the other. The comparator monitors the voltage levels of each pair of nodes and generates a trigger signal upon detection of the voltage levels at a pair of nodes passing each other.

Abstract: A method to calibrate I/O cell current has been described. The method includes setting a global control value provided to the I/O cells. Then, for each I/O cell, the method includes comparing the logic voltage at the output pad of the I/O cell with a reference voltage, and sinking more current at the output pad by enabling additional driver bits associated with the I/O cell if the logic voltage is higher than the reference voltage, or sinking less current at the output pad by disabling additional driver bits associated with the I/O cell if the logic voltage is lower than the reference voltage.

Abstract: A local driver circuit to drive a logic voltage at an output pad includes an adder having K bits to add a K-bit control value to a local value, the adder producing a K-bit calibrated value. The circuit further includes K field-effect transistors (FETs), the drain of each FET being coupled to the output pad, and logic circuitry to perform a logical-AND function between a data input and the K-bit calibrated value. The logic circuitry providing a K-bit output with each of the K output bits being coupled to the gate of a corresponding one of the FETs. A comparator produces a correction value from a comparison of the logic voltage at the output pad and a reference voltage. A control unit sets a least significant bit (LSB) portion of the local value responsive to the correction value so as to make the logic voltage at the output pad in the reference voltage substantially equal.

Abstract: An apparatus which generates a clock signal includes a first phase mixer which generates an initial clock signal based on a first set of reference clocks and a buffer which adds a first predetermined delay to the initial clock signal to produce a first clock signal. A phase detection circuit detects a difference in phase between the first clock signal and a master clock signal, and a control circuit selects a second set of reference clocks based on the difference in phase and a second predetermined delay. A second phase mixer generates an output clock signal based on the second set of reference clocks.

Abstract: A high-voltage differential input receiver interfaces with an external channel. The differential input receiver includes a first stage, a second stage, and a third stage, which incrementally reduce in stages the common mode of a differential signal received from the external channel. During a power-down mode, clamping circuits in the differential input receiver clamp the voltage at nodes in the differential input receiver, and clamp the differential output from the first stage, to a predetermined voltage to prevent electrical overstress of oxide layers of n-channel and p-channel devices in the differential input receiver. Consequently, electrical overstress of oxide layers is prevented, and the voltage swing level of inputs from the external channel is reduced in stages from a higher voltage level to a lower voltage level.

Abstract: A device on a source synchronous data bus includes a clock generation circuit which generates transmit and receive clock signals for transmitting and receiving data. The device sends data in quadrature phase relationship with the bus clock signal and receives data in phase with the bus clock signal.