Patents by Inventor Jonathan H. Orchard-Webb

Jonathan H. Orchard-Webb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6204164
    Abstract: In a method of making electrical connections to an integrated chip, an oxide layer is formed on the surface of the chip and a substrate carrying electrical connections. The conductors on the chip are accurately aligned with the conductors on the substrate. An oxide layer formed on the surface of the chip is then fusion bonded to an oxide layer on the substrate and voids remaining between the conductors filled with a conductive material. This method removes the limitation imposed by the large pad size needed for conventional techniques.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: March 20, 2001
    Assignee: Mitel Corporation
    Inventor: Jonathan H. Orchard-Webb
  • Patent number: 5568346
    Abstract: A input circuit provides ESD protection to an integrated circuit comprising a V.sub.dd pad, a V.sub.ss pad, a plurality of input and output pads, a V.sub.dd power rail, and a V.sub.ss power rail. A large diode sufficient to carry ESD current is placed directly between the V.sub.ss pad and the V.sub.dd power rail, and the input pads are connected to the V.sub.dd power rail through respective diodes.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: October 22, 1996
    Assignee: Mitel Corporation
    Inventor: Jonathan H. Orchard-Webb
  • Patent number: 5557130
    Abstract: An arrangement for protecting an input of a monolithic integrated circuit against ESD events, comprises a thick field bipolar main transistor adapted to breakdown under ESD stress to dissipate ESD energy, a thin field bipolar main transistor adapted to breakdown under ESD stress, and an attenuator resistor. The thin field transistor has a lower breakdown voltage than the thick field transistor whereby for an ESD event of a given polarity, the thin field transistor breaks down before the thick field transistor. During an ESD event current, the thin field device responds rapidly to the fast edge of an ESD transient and thereby shunts current that the thick field device is too slow to respond to.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: September 17, 1996
    Assignee: Mitel Corporation
    Inventor: Jonathan H. Orchard-Webb
  • Patent number: 5166764
    Abstract: An integrated circuit has an input protection device including a bipolar transistor to shunt current away from sensitive areas of the circuit during an e.s.d. event. The bipolar transistor includes floating electrodes on the base to define an equipotential base region so that the effective size of the emitter, and hence the currently handling capability of the transistor, is increased.
    Type: Grant
    Filed: July 15, 1991
    Date of Patent: November 24, 1992
    Assignee: Mitel Corporation
    Inventor: Jonathan H. Orchard-Webb