Abstract: A process for purifying a composition comprising water, a target substance, impurities and optionally cells, the process comprising the steps (A) and (B): (A) preparing a liquid feedstock by performing step (Ai) and/or (Aii) on the composition: (Ai) removing at least some of the cells from the composition; (Aii) concentrating the composition by removing water therefrom; and (B) passing the liquid feedstock through an apparatus comprising at least two processing units, each such unit producing a product stream containing purified target substance and optionally a waste stream comprising at least some of the impurities, wherein each unit comprises specified components (i) to (v). The units may be essentially the same except for a device they contain, leading to advantages in terms of simplicity, cost and ease of operation, lower risk of operator error, easier maintenance and lower inventory of spare parts.

Abstract: Apparatus for purifying a liquid comprising a target substance comprising at least two units arranged in series such that the feed stream of the second and any subsequent units comprises the product stream from a downstream unit, wherein each unit comprises specified components (i) to (vi), including a a switchable bypass assembly. Also claimed are the units and a flowpath assembly. The units may be essentially the same except for a device they contain, leading to advantages in terms of simplicity, cost and ease of operation, lower risk of operator error, easier maintenance and lower inventory of spare parts.

Abstract: A process for purifying a liquid feedstock comprising a monoclonal antibody and impurities, the process comprising passing the liquid feedstock through an apparatus comprising at least two processing units, each such unit producing a product stream containing purified monoclonal antibody and optionally a waste stream comprising at least some of the impurities, wherein each unit comprises specified components (i) to (v) which include a multiple inlet flow-controller comprising two or more variable flow inlet valves for in situ production of a bioprocessing liquid by combining at least two liquids in a desired ratio. One of the units performs chromatography and another performs viral inactivation. The units may be essentially the same except for a device they contain, leading to advantages in terms of simplicity, cost and ease of operation, lower risk of operator error, easier maintenance and lower inventory of spare parts.

Abstract: An IC that includes a contiguous standard cell area with a 4x3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: Apparatus for processing a liquid comprising a target substance, preferably a biomolecule, is provided.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas.

Abstract: Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern.

Abstract: An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein. In some embodiments, the contiguous standard cell area may further include: fourth and fifth TS-GATE-short-configured test area geometries, and/or other test area geometries, such as tip-to-tip-short, tip-to-side-short, diagonal-short, corner-short, interlayer-overlap-short, via-chamfer-short, merged-via-short, snake-open, stitch-open, via-open, or metal-island-open.

Abstract: The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.

Abstract: Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.

Abstract: An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts.

Abstract: An improved standard cell chip, library and/or process ensures that there is adequate spacing between TSCUT jogs and nearby gate contacts to avoid inadvertent shorts/leakages that can degrade manufacturing yield or performance.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and corner short test areas.

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas.