Patents by Inventor Jonathan Hale Hammond
Jonathan Hale Hammond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11069590Abstract: The present disclosure relates to a wafer-level fan-out package that includes a first thinned die, a second die, a multilayer redistribution structure underneath the first thinned die and the second die, a first mold compound over the second die, a second mold compound over the multilayer redistribution structure, and around the first thinned die and the second die, and a third mold compound. The second mold compound extends beyond the first thinned die to define an opening within the second mold compound and over the first thinned die, such that a top surface of the first thinned die is at a bottom of the opening. A top surface of the first mold compound and a top surface of the second mold compound are coplanar. The third mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: June 27, 2019Date of Patent: July 20, 2021Assignee: Qorvo US, Inc.Inventors: Jonathan Hale Hammond, Julio C. Costa, Jon Chadwick
-
Patent number: 10964554Abstract: The present disclosure relates to a packaging process to enhance performance of a wafer-level package. The disclosed package includes multiple mold compounds, a multilayer redistribution structure, and a thinned die with a device layer and die bumps underneath the device layer. The multilayer redistribution structure includes package contacts at a bottom of the multilayer redistribution structure and redistribution interconnects connecting the die bumps to the package contacts. A first mold compound resides around the thinned die to encapsulate sidewalls of the thinned die, and extends beyond a top surface of the thinned die to define an opening over the thinned die. A second mold compound resides between the multilayer redistribution structure and the first mold compound to encapsulate a bottom surface of the device layer and each die bump. A third mold compound fills the opening and is in contact with the top surface of the thinned die.Type: GrantFiled: June 27, 2019Date of Patent: March 30, 2021Assignee: Qorvo US, Inc.Inventors: Jonathan Hale Hammond, Julio C. Costa
-
Patent number: 10950518Abstract: The present disclosure relates to a wafer-level fan-out package that includes a first thinned die, a second die, a multilayer redistribution structure underneath the first thinned die and the second die, a first mold compound over the second die, a second mold compound over the multilayer redistribution structure, and around the first thinned die and the second die, and a third mold compound. The second mold compound extends beyond the first thinned die to define an opening within the second mold compound and over the first thinned die, such that a top surface of the first thinned die is at a bottom of the opening. A top surface of the first mold compound and a top surface of the second mold compound are coplanar. The third mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: June 27, 2019Date of Patent: March 16, 2021Assignee: Qorvo US, Inc.Inventors: Jonathan Hale Hammond, Julio C. Costa, Jon Chadwick
-
Patent number: 10903132Abstract: The present disclosure relates to a wafer-level fan-out package that includes a first thinned die, a second die, a multilayer redistribution structure underneath the first thinned die and the second die, a first mold compound over the second die, a second mold compound over the multilayer redistribution structure, and around the first thinned die and the second die, and a third mold compound. The second mold compound extends beyond the first thinned die to define an opening within the second mold compound and over the first thinned die, such that a top surface of the first thinned die is at a bottom of the opening. A top surface of the first mold compound and a top surface of the second mold compound are coplanar. The third mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: June 27, 2019Date of Patent: January 26, 2021Assignee: Qorvo US, Inc.Inventors: Jonathan Hale Hammond, Julio C. Costa, Jon Chadwick
-
Patent number: 10882740Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: December 4, 2019Date of Patent: January 5, 2021Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
-
Patent number: 10804179Abstract: The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.Type: GrantFiled: October 23, 2018Date of Patent: October 13, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jan Edward Vandemeer, Jonathan Hale Hammond, Merrill Albert Hatcher, Jr., Jon Chadwick
-
Patent number: 10773952Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: May 22, 2017Date of Patent: September 15, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
-
Patent number: 10770253Abstract: Microelectromechanical system (MEMS) switches that provide low contact resistance over a large number of open and close contact cycles are disclosed. A MEMS switch device may include a plurality of parallel MEMS switches with a first MEMS switch that is configured differently in such a manner to close first and/or open last during open and close cycles. In this regard, the first MEMS switch may experience increased contact resistance over a large number of open and close cycles while other MEMS switches maintain a low contact resistance. In certain embodiments, the first MEMS switch is controlled by a different control signal to open and close differently than the other MEMS switches. In certain embodiments, a common control signal controls a plurality of MEMS switches and the first MEMS switch is mechanically different such that it opens and closes differently than other MEMS switches.Type: GrantFiled: October 30, 2018Date of Patent: September 8, 2020Assignee: Qorvo US, Inc.Inventors: Nadim Khlat, Jonathan Hale Hammond
-
Patent number: 10679918Abstract: The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.Type: GrantFiled: October 23, 2018Date of Patent: June 9, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jan Edward Vandemeer, Jonathan Hale Hammond, Merrill Albert Hatcher, Jr., Jon Chadwick
-
Patent number: 10676348Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: May 22, 2017Date of Patent: June 9, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
-
Patent number: 10636720Abstract: The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.Type: GrantFiled: October 23, 2018Date of Patent: April 28, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jan Edward Vandemeer, Jonathan Hale Hammond, Merrill Albert Hatcher, Jr., Jon Chadwick
-
Publication number: 20200115220Abstract: The present disclosure relates to a wafer-level fan-out package that includes a first thinned die, a second die, a multilayer redistribution structure underneath the first thinned die and the second die, a first mold compound over the second die, a second mold compound over the multilayer redistribution structure, and around the first thinned die and the second die, and a third mold compound. The second mold compound extends beyond the first thinned die to define an opening within the second mold compound and over the first thinned die, such that a top surface of the first thinned die is at a bottom of the opening. A top surface of the first mold compound and a top surface of the second mold compound are coplanar. The third mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: ApplicationFiled: June 27, 2019Publication date: April 16, 2020Inventors: Jonathan Hale Hammond, Julio C. Costa, Jon Chadwick
-
Publication number: 20200118838Abstract: The present disclosure relates to a packaging process to enhance performance of a wafer-level package. The disclosed package includes multiple mold compounds, a multilayer redistribution structure, and a thinned die with a device layer and die bumps underneath the device layer. The multilayer redistribution structure includes package contacts at a bottom of the multilayer redistribution structure and redistribution interconnects connecting the die bumps to the package contacts. A first mold compound resides around the thinned die to encapsulate sidewalls of the thinned die, and extends beyond a top surface of the thinned die to define an opening over the thinned die. A second mold compound resides between the multilayer redistribution structure and the first mold compound to encapsulate a bottom surface of the device layer and each die bump. A third mold compound fills the opening and is in contact with the top surface of the thinned die.Type: ApplicationFiled: June 27, 2019Publication date: April 16, 2020Inventors: Jonathan Hale Hammond, Julio C. Costa
-
Publication number: 20200102217Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: ApplicationFiled: December 4, 2019Publication date: April 2, 2020Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, JR., Jonathan Hale Hammond
-
Patent number: 10600711Abstract: The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.Type: GrantFiled: October 23, 2018Date of Patent: March 24, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jan Edward Vandemeer, Jonathan Hale Hammond, Merrill Albert Hatcher, Jr., Jon Chadwick
-
Patent number: 10589993Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: May 22, 2017Date of Patent: March 17, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
-
Patent number: 10549988Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: May 22, 2017Date of Patent: February 4, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
-
Patent number: 10529639Abstract: The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.Type: GrantFiled: October 23, 2018Date of Patent: January 7, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jan Edward Vandemeer, Jonathan Hale Hammond, Merrill Albert Hatcher, Jr., Jon Chadwick
-
Patent number: 10486965Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer formed from glass materials. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: August 14, 2017Date of Patent: November 26, 2019Assignee: Qorvo US, Inc.Inventors: Jan Edward Vandemeer, Jonathan Hale Hammond, Julio C. Costa
-
Patent number: 10486963Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: August 14, 2017Date of Patent: November 26, 2019Assignee: Qorvo US, Inc.Inventors: Merrill Albert Hatcher, Jr., Jonathan Hale Hammond, Jon Chadwick, Julio C. Costa, Jan Edward Vandemeer