Patents by Inventor Jonathan HINKE

Jonathan HINKE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS BOUND BY GATE CUTS
    Publication number: 20250227960
    Abstract: Integrated circuit structures having fin isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure.
    Type: Application
    Filed: March 28, 2025
    Publication date: July 10, 2025
    Inventors: Leonard P. GULER, Sean PURSEL, Dan S. LAVRIC, Allen B. GARDINER, Jonathan HINKE, Wonil CHUNG
  • INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS BOUND BY GATE CUTS
    Publication number: 20240105804
    Abstract: Integrated circuit structures having fin isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Inventors: Leonard P. GULER, Sean PURSEL, Dan S. LAVRIC, Allen B. GARDINER, Jonathan HINKE, Wonil CHUNG