Abstract: An apparatus includes a plurality of data buffer and multiplexer devices that communicate data signals with the host memory controller at twice the clock rate that the data buffer and multiplexer devices communicate first and second data signals with first and second memory modules. The apparatus further includes a registered clock driver that communicates host command and address signals at twice the clock rate that the registered clock driver communicates first and second command and address signals with the first and second memory modules. The second data signals and second command and address signals may be directed to a data conversion module that converts the signals to be communicated over a serial computer expansion bus with the second memory module.

Abstract: An apparatus includes a plurality of data buffer and multiplexer devices that communicate data signals with the host memory controller at twice the clock rate that the data buffer and multiplexer devices communicate first and second data signals with first and second memory modules. The apparatus further includes a registered clock driver that communicates host command and address signals at twice the clock rate that the registered clock driver communicates first and second command and address signals with the first and second memory modules. The second data signals and second command and address signals may be directed to a data conversion module that converts the signals to be communicated over a serial computer expansion bus with the second memory module.

Abstract: A computer-implemented method and a serially-attached memory device for performing the method are provided. The method includes a memory device controller receiving data over an error-protected serial link from a host processor, wherein the memory device controller is included in a serially-attached memory device along with memory media coupled to the memory device controller. The method further includes the memory device controller storing the received data in the memory media coupled to the memory device controller, the memory device controller calculating error correction code for the received data, and the memory device controller storing the error correction code in the memory media coupled to the memory device controller.

Abstract: A far memory device includes a far memory controller, a memory device coupled to the controller, a first port coupled to the far memory controller to support communication with a host processor over a first serial computer expansion bus, and a second port coupled to the far memory controller to support communication with a non-volatile data storage drive over a second serial computer expansion bus. The far memory device serves as a cache between the host processor and the non-volatile data storage drive and may perform aspects of cache management on behalf of the host processor.

Abstract: A computer-implemented method and a serially-attached memory device for performing the method are provided. The method includes a memory device controller receiving data over an error-protected serial link from a host processor, wherein the memory device controller is included in a serially-attached memory device along with memory media coupled to the memory device controller. The method further includes the memory device controller storing the received data in the memory media coupled to the memory device controller, the memory device controller calculating error correction code for the received data, and the memory device controller storing the error correction code in the memory media coupled to the memory device controller.

Abstract: A computer program product provides program instructions that are executable by a processor to cause the processor to perform various operations. The operations may include monitoring a performance metric for a workload instance being executed by a composed system within a pool of composable resources in a composable computing system. The composed system includes a compute resource and an associated hardware resource selected from a data storage resource, a memory resource and/or a graphic processing resource. A service level agreement is identified for the workload instance, wherein the agreement includes a minimum level of the performance metric that the composed system must provide to support the workload instance. A power cap may be imposed on the compute resource, and a power cap may be imposed on the associated hardware resource by sending a power capping command to a baseboard management controller on a server including the associated hardware resource.

Abstract: A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.

Abstract: A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.

Abstract: An apparatus or hybrid connector includes a connector assembly and a plurality of electronically conductive elements supported by the connector assembly. The connector assembly further includes a first connector for connecting with a first printed circuit board (PCB), a second connector for connecting with a second PCB, and a wire termination connected to a high-speed communication cable. The second connector forms a right angle with the first connector, and the second connector is oriented to connect with the second PCB in an orthogonal orientation to the first PCB. The conductive elements have a first end terminating in the second card edge connector, whereas a first portion of the conductive elements have a second end terminating in the wire termination and a second portion of the conductive elements have a second end terminating in the first connector. Multiple hybrid connectors may be connected to a first printed circuit board.

Abstract: A random number generating unit is disclosed. The random number generating unit comprises an external containment casing and a measurement cone within the external containment casing, to which liquid detection contacts are attached. One or more terminals on a random number generation integrated circuit, which terminals connect to the liquid detection contacts are included, as is a primary reservoir connected to a secondary reservoir containing a pump and a dropper to provide a bead of liquid from the pump, wherein the bead falls on the measurement cone to be detected by the liquid detection contacts and then fall into the primary reservoir.