Patents by Inventor Jonathan Iloreta
Jonathan Iloreta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250224344Abstract: Methods and systems for using pre-process measurement data to train post-process, machine learning (ML) based measurement models are described herein. In one aspect, a post-process, ML based measurement model is trained using reference data derived from actual reference measurements and estimated reference data generated by a trained mapping model. The trained mapping model maps measured values of parameters of interest at a pre-process state to estimated reference values at the post-process state. In this manner, the reference data employed to train a ML based measurement model is augmented based on pre-process measurement data. In another aspect, measurements of complex semiconductor structures are based on a combined measurement model including trained pre-process and post-process measurement models. Pre-process measurement data is employed directly as part of a combined ML based measurement and indirectly as part of the training data set for the combined ML based measurement model.Type: ApplicationFiled: June 13, 2024Publication date: July 10, 2025Inventors: Houssam Chouaib, Anderson Chou, HaoMiao Chang, Brooks Hsiao, Ben Hsieh, James Chuang, Zhengquan Tan, Derrick Shaughnessy, Jonathan Iloreta
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Publication number: 20250053096Abstract: Methods and systems for generating measurement models of complex semiconductor structures based on re-useable, parametric models are presented herein. In some embodiments, the re-useable, parametric models enable measurement of high aspect ratio (HAR) structures having complex shape profiles. In these embodiments, a re-useable, parametric model includes multiple geometric sections each characterized by a different shape profile. Each shape profile is parameterized by at least one shape parameter. In a further aspect, at least one of the multiple geometric sections includes a plurality of subsections. In some other embodiments, the re-useable, parametric models enable measurement of nanowire based semiconductor structures. The re-useable, parametric models described herein are useful for generating measurement models for both optical metrology and x-ray metrology, e.g., soft x-ray metrology and hard x-ray metrology.Type: ApplicationFiled: August 7, 2023Publication date: February 13, 2025Inventors: Houssam Chouaib, Tianrong Zhan, Jonathan Iloreta, Teng Gu, Andrei V. Shchegrov
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Patent number: 11099137Abstract: A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an augmented-reality or virtual-reality (AR/VR) image of the model that shows a 3D shape of the model and provides the AR/VR image to an AR/VR viewing device for display.Type: GrantFiled: August 28, 2020Date of Patent: August 24, 2021Assignee: KLA CorporationInventors: Aaron J. Rosenberg, Jonathan Iloreta, Thaddeus G. Dziura, Antonio Gellineau, Yin Xu, Kaiwen Xu, John Hench, Abhi Gunde, Andrei Veldman, Liequan Lee, Houssam Chouaib
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Publication number: 20200393386Abstract: A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an augmented-reality or virtual-reality (AR/VR) image of the model that shows a 3D shape of the model and provides the AR/VR image to an AR/VR viewing device for display.Type: ApplicationFiled: August 28, 2020Publication date: December 17, 2020Inventors: Aaron J. Rosenberg, Jonathan Iloreta, Thaddeus G. Dziura, Antonio Gellineau, Yin Xu, Kaiwen Xu, John Hench, Abhi Gunde, Andrei Veldman, Liequan Lee, Houssam Chouaib
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Patent number: 10794839Abstract: A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an image of the model that shows a 3D shape of the model and provides the image to a device for display.Type: GrantFiled: February 22, 2019Date of Patent: October 6, 2020Assignee: KLA CorporationInventors: Aaron J. Rosenberg, Jonathan Iloreta, Thaddeus G. Dziura, Antonio Gellineau, Yin Xu, Kaiwen Xu, John Hench, Abhi Gunde, Andrei Veldman, Liequan Lee, Houssam Chouaib
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Publication number: 20200271595Abstract: A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an image of the model that shows a 3D shape of the model and provides the image to a device for display.Type: ApplicationFiled: February 22, 2019Publication date: August 27, 2020Inventors: Aaron J. Rosenberg, Jonathan Iloreta, Thaddeus G. Dziura, Antonio Gellineau, Yin Xu, Kaiwen Xu, John Hench, Abhi Gunde, Andrei Veldman, Liequan Lee, Houssam Chouaib
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Patent number: 9553033Abstract: Methods and tools for generating measurement models of complex device structures based on re-useable, parametric models are presented. Metrology systems employing these models are configured to measure structural and material characteristics associated with different semiconductor fabrication processes. The re-useable, parametric sub-structure model is fully defined by a set of independent parameters entered by a user of the model building tool. All other variables associated with the model shape and internal constraints among constituent geometric elements are pre-defined within the model. In some embodiments, one or more re-useable, parametric models are integrated into a measurement model of a complex semiconductor device. In another aspect, a model building tool generates a re-useable, parametric sub-structure model based on input from a user.Type: GrantFiled: January 12, 2015Date of Patent: January 24, 2017Assignee: KLA-Tencor CorporationInventors: Jonathan Iloreta, Matthew A. Laffin, Leonid Poslavsky, Torsten Kaack, Qiang Zhao, Lie-Quan Lee
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Patent number: 9127927Abstract: Provided are optimized scatterometry techniques for evaluating a diffracting structure. In one embodiment, a method includes computing a finite-difference derivative of a field matrix with respect to first parameters (including a geometric parameter of the diffracting structure), computing an analytic derivative of the Jones matrix with respect to the field matrix, computing a derivative of the Jones matrix with respect to the first parameters, and computing a finite-difference derivative of the Jones matrix with respect to second parameters (including a non-geometric parameter). In one embodiment, a method includes generating a transfer matrix having Taylor Series approximations for elements, and decomposing the field matrix into two or more smaller matrices based on symmetry between the incident light and the diffracting structure.Type: GrantFiled: December 12, 2012Date of Patent: September 8, 2015Assignee: KLA-Tencor CorporationInventors: Jonathan Iloreta, Paul Aoyagi, Hanyou Chu, Jeffrey Chard, Peilin Jiang, Mikhail Sushchik, Leonid Poslavsky, Philip D. Flanner, III
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Publication number: 20150199463Abstract: Methods and tools for generating measurement models of complex device structures based on re-useable, parametric models are presented. Metrology systems employing these models are configured to measure structural and material characteristics associated with different semiconductor fabrication processes. The re-useable, parametric sub-structure model is fully defined by a set of independent parameters entered by a user of the model building tool. All other variables associated with the model shape and internal constraints among constituent geometric elements are pre-defined within the model. In some embodiments, one or more re-useable, parametric models are integrated into a measurement model of a complex semiconductor device. In another aspect, a model building tool generates a re-useable, parametric sub-structure model based on input from a user.Type: ApplicationFiled: January 12, 2015Publication date: July 16, 2015Inventors: Jonathan Iloreta, Matthew A. Laffin, Leonid Poslavsky, Torsten Kaack, Qiang Zhao, Lie-Quan Lee
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Publication number: 20130158948Abstract: Provided are optimized scatterometry techniques for evaluating a diffracting structure. In one embodiment, a method includes computing a finite-difference derivative of a field matrix with respect to first parameters (including a geometric parameter of the diffracting structure), computing an analytic derivative of the Jones matrix with respect to the field matrix, computing a derivative of the Jones matrix with respect to the first parameters, and computing a finite-difference derivative of the Jones matrix with respect to second parameters (including a non-geometric parameter). In one embodiment, a method includes generating a transfer matrix having Taylor Series approximations for elements, and decomposing the field matrix into two or more smaller matrices based on symmetry between the incident light and the diffracting structure.Type: ApplicationFiled: December 12, 2012Publication date: June 20, 2013Inventors: Jonathan Iloreta, Paul Aoyagi, Hanyou Chu, Jeffrey Chard, Peilin Jiang, Mikhail Sushchik, Leonid Poslavsky, Phillip D. Flanner, III