Patents by Inventor Jonathan J. Chew
Jonathan J. Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8762999Abstract: In general, embodiments of the invention relates to a method for conveying hardware resources from a host (OS) executing on a computer system. The method includes obtaining host hardware information by the host OS, wherein the host hardware information specifies a plurality of physical hardware components of the computer system, sending the host hardware information to a guest OS executing within the host OS, generating, by the guest OS, a resource request using the host hardware information, sending, by the guest OS, the resource request to the host OS, and in response to receiving the resource request, allocating, by the host OS, guest hardware resources, where the guest hardware resources include at least one of the physical hardware components in the resource request.Type: GrantFiled: September 27, 2007Date of Patent: June 24, 2014Assignee: Oracle America, Inc.Inventors: Darrin P. Johnson, Eric C. Saxe, Jonathan J. Chew
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Patent number: 8539494Abstract: A method for scheduling a new thread involves identifying a criticality level of the new thread, selecting a processor group according to the criticality level of the new thread and an existing assigned utilization level of the processor group to obtain a selected processor group, increasing an assigned utilization level of the selected processor group based on the new thread, and executing the new thread by the selected processor group.Type: GrantFiled: January 31, 2011Date of Patent: September 17, 2013Assignee: Oracle International CorporationInventors: Eric C. Saxe, Rafael Vanoni Polanczyk, Jonathan J. Chew, Steven Sistare
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Publication number: 20120198461Abstract: A method for scheduling a new thread involves identifying a criticality level of the new thread, selecting a processor group according to the criticality level of the new thread and an existing assigned utilization level of the processor group to obtain a selected processor group, increasing an assigned utilization level of the selected processor group based on the new thread, and executing the new thread by the selected processor group.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Eric C. Saxe, Rafael Vanoni Polanczyk, Jonathan J. Chew, Steven Sistare
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Patent number: 8205100Abstract: A method for power managing hardware. The method includes determining hardware to power manage, sending a tracing request from a power management control to a tracing framework to obtain usage data of the hardware, and identifying a first probe to obtain first tracing data corresponding to the usage data in a first hardware control software component, where the first hardware control software is configured to interact with the hardware. The method further includes enabling the first probe, obtaining the first tracing data from the first probe, where the first tracing data is obtained when the first probe is encountered during execution of the first hardware control software, and modifying operation of the hardware using the first tracing data.Type: GrantFiled: June 19, 2008Date of Patent: June 19, 2012Assignee: Oracle America, Inc.Inventors: Eric C. Saxe, Darrin P. Johnson, Jonathan J. Chew
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Patent number: 8156495Abstract: A device, system, and method are directed towards managing threads and components in computer system with one or more processing units. A processor group has an associated hierarchical structure containing nodes that may correspond to processing units, hardware components, or abstractions. The processor group hierarchy may be used to assign one or more threads to one or more processing units, by traversing the hierarchy based on various factors. The factor may include load balancing, affinity, sharing of components, loads, capacities, or other characteristics of components or threads. A processor group hierarchy may be used in conjunction with a designated processor set.Type: GrantFiled: January 17, 2008Date of Patent: April 10, 2012Assignee: Oracle America, Inc.Inventors: Jonathan J. Chew, Eric Christopher Saxe
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Publication number: 20090320000Abstract: A method for power managing hardware. The method includes determining hardware to power manage, sending a tracing request from a power management control to a tracing framework to obtain usage data of the hardware, and identifying a first probe to obtain first tracing data corresponding to the usage data in a first hardware control software component, where the first hardware control software is configured to interact with the hardware. The method further includes enabling the first probe, obtaining the first tracing data from the first probe, where the first tracing data is obtained when the first probe is encountered during execution of the first hardware control software, and modifying operation of the hardware using the first tracing data.Type: ApplicationFiled: June 19, 2008Publication date: December 24, 2009Applicant: SUN MICROSYSTEMS, INC.Inventors: Eric C. Saxe, Darrin P. Johnson, Jonathan J. Chew
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Publication number: 20090187915Abstract: A device, system, and method are directed towards managing threads and components in computer system with one or more processing units. A processor group has an associated hierarchical structure containing nodes that may correspond to processing units, hardware components, or abstractions. The processor group hierarchy may be used to assign one or more threads to one or more processing units, by traversing the hierarchy based on various factors. The factor may include load balancing, affinity, sharing of components, loads, capacities, or other characteristics of components or threads. A processor group hierarchy may be used in conjunction with a designated processor set.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Applicant: SUN MICROSYSTEMS, INC.Inventors: Jonathan J. Chew, Eric Christopher Saxe
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Publication number: 20090089780Abstract: In general, embodiments of the invention relates to a method for conveying hardware resources from a host (OS) executing on a computer system. The method includes obtaining host hardware information by the host OS, wherein the host hardware information specifies a plurality of physical hardware components of the computer system, sending the host hardware information to a guest OS executing within the host OS, generating, by the guest OS, a resource request using the host hardware information, sending, by the guest OS, the resource request to the host OS, and in response to receiving the resource request, allocating, by the host OS, guest hardware resources, where the guest hardware resources include at least one of the physical hardware components in the resource request.Type: ApplicationFiled: September 27, 2007Publication date: April 2, 2009Applicant: SUN MICROSYSTEMS, INC.Inventors: Darrin P. Johnson, Eric C. Saxe, Jonathan J. Chew
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Patent number: 7149863Abstract: In a computer system, a descriptive memory allocation system is described having a memory policy allocation module for setting memory allocation policies by an operating system in response to descriptive resource use requirements provided by an application requesting access to a specified address range in memory. The descriptive memory allocation system includes a descriptive resource allocator that uses descriptive memory use advice provided by an application to decide how to allocate memory to the application. The descriptive resource allocator includes memory allocation policies that may be set by the operating system after the operating system has determined the appropriate allocation scheme to implement based on an allocation advice provided by a requesting after the application. The application in providing its descriptive memory use information does not specify a specific allocation policy the operating system should use to allocate memory to it.Type: GrantFiled: October 8, 2003Date of Patent: December 12, 2006Assignee: Sun Microsystems, Inc.Inventors: Jonathan J. Chew, Bart Smaalders