Patents by Inventor Jonathan J. Strand

Jonathan J. Strand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395115
    Abstract: Methods, systems, and devices for robust functionality for memory management associated with high-temperature storage are described. A memory device may apply a pattern (e.g., an imprint conditioning or deletion pattern) to at least a portion of memory cells of a memory array associated with a memory device before or after a power state procedure. The memory device may determine the pattern from various possible patterns, where the pattern may indicate a data state for each memory cell of the portion of memory cells. The pattern may indicate a same data state for each memory cell, an alternating data state for each memory cell, or an asymmetric switching pattern over a plurality of cycles, or any combination thereof. The memory device may write a respective logic value to at least some of the one or more memory cells of the portion of memory cells according to the pattern.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Angelo Visconti, Jonathan J. Strand
  • Patent number: 11749330
    Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Angelo Visconti, Riccardo Pazzocco, Jonathan J. Strand, Kevin T. Majerus
  • Publication number: 20230253064
    Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Application
    Filed: March 31, 2023
    Publication date: August 10, 2023
    Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
  • Publication number: 20230187010
    Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 15, 2023
    Inventors: Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman
  • Patent number: 11631473
    Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: April 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
  • Publication number: 20230114735
    Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.
    Type: Application
    Filed: November 7, 2022
    Publication date: April 13, 2023
    Inventors: Angelo Visconti, Riccardo Pazzocco, Jonathan J. Strand, Kevin T. Majerus
  • Patent number: 11557371
    Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman
  • Patent number: 11514968
    Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Angelo Visconti, Riccardo Pazzocco, Jonathan J. Strand, Kevin T. Majerus
  • Publication number: 20220199155
    Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 23, 2022
    Inventors: Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman, Jonathan D. Harms
  • Publication number: 20220044759
    Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Application
    Filed: August 11, 2021
    Publication date: February 10, 2022
    Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
  • Patent number: 11217303
    Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman, Jonathan D. Harms
  • Publication number: 20210319843
    Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Application
    Filed: April 27, 2021
    Publication date: October 14, 2021
    Inventors: Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman
  • Publication number: 20210304805
    Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Inventors: Angelo Visconti, Riccardo Pazzocco, Jonathan J. Strand, Kevin T. Majerus
  • Patent number: 11094394
    Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
  • Patent number: 10998080
    Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman
  • Publication number: 20210089385
    Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventors: Sukneet Singh Basuta, Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand
  • Publication number: 20210090680
    Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
  • Publication number: 20210090641
    Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventors: Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman, Jonathan D. Harms
  • Publication number: 20210090681
    Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventors: Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman