Patents by Inventor Jonathan K. Ross
Jonathan K. Ross has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240082085Abstract: An overhead arm assembly for a patient support apparatus includes a user interface device. The user interface device has a support structure for supporting a personal digital assistant and a charging port for personal digital assistant.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: Robert M. Zerhusen, Jonathan K. Moenter, Joshua L. Meyer, Robert D. Ross, John G. Byers, Matthew R. Knue
-
Patent number: 9223600Abstract: A data processor includes a redirection dynamic address redirection table (DART) for redirecting instruction fetches from an original memory location with an original address to a target memory location with a target address.Type: GrantFiled: May 7, 2007Date of Patent: December 29, 2015Assignee: Hewlett Packard Enterprise Development LPInventors: Jonathan K. Ross, Dale C. Morris, James M. Hull
-
Patent number: 7765238Abstract: A method for mapping an active entry within a virtually hashed page table is disclosed. An active entry within a virtually hashed page table is populated. A link table for locating a link at an offset from an active entry is maintained. This link table continues to be maintained as a valid link table until an occupied head bucket threshold is exceeded or a collision has occurred.Type: GrantFiled: April 30, 2007Date of Patent: July 27, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christophe De Dinechin, Todd J. Kjos, Jonathan K. Ross
-
Patent number: 7613847Abstract: A computer system comprises a physical computer and a virtual machine monitor executable on the physical computer and configured to create an emulation of at least one guest operating system adapted to control the physical computer. The computer system further comprises a host executable on the physical computer that manages physical resources coupled to the physical computer on behalf of the virtual machine monitor and the at least one guest operating system. The host is adapted to virtualize a Peripheral Component Interconnect (PCI) configuration address space whereby the at least one guest operating system controls PCI input/output (I/O) devices directly and in absence of I/O emulation.Type: GrantFiled: May 16, 2006Date of Patent: November 3, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Todd J. Kjos, Jonathan K. Ross, Christophe De Dinechin
-
Patent number: 7451249Abstract: Method and apparatus for allowing a direct memory access unit to have access to a virtual address space is accomplished by receiving a request for memory access from the direct memory access device; determining a device identifier according to the received request for memory access; determining a memory protection schema according to the determined device identifier; and granting the direct memory access unit access to memory in accordance with the determined memory protection schema.Type: GrantFiled: March 16, 2006Date of Patent: November 11, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Joe P. Cowan, Matthew B. Lovell, Leith L. Johnson, Jonathan K. Ross
-
Publication number: 20080270349Abstract: A method for mapping an active entry within a virtually hashed page table is disclosed. An active entry within a virtually hashed page table is populated. A link table for locating a link at an offset from an active entry is maintained. This link table continues to be maintained as a valid link table until an occupied head bucket threshold is exceeded or a collision has occurred.Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Inventors: Christophe De Dinechin, Todd J. Kjos, Jonathan K. Ross
-
Patent number: 7426728Abstract: One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt mask value is written to the TPR. In addition, the interrupt mask value is also written into a shadow copy of the TPR. The shadow copy is written each time that the TPR is written. Another embodiment disclosed relates to a method of reducing a latency to read a TPR of an IPF type microprocessor. When a command is received to read an interrupt mask value from the TPR, the interrupt mask value is read from the shadow copy at a memory location, instead of from the task priority register itself.Type: GrantFiled: September 24, 2003Date of Patent: September 16, 2008Assignee: Hewlett-Packard Development, L.P.Inventors: Christopher Philip Ruemmler, Jonathan K. Ross
-
Patent number: 7421689Abstract: Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.Type: GrantFiled: October 28, 2003Date of Patent: September 2, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jonathan K. Ross, Dale Morris, Donald C. Soltis, Jr., Rohit Bhatia, Eric Delano
-
Patent number: 7340630Abstract: A multiprocessor computer system comprises multiple data processors, each with an internal clock for providing time stamps to application software. The processors take turns as synchronization masters. The present master transmits a “request” time stamp (indicating the time of transmission according to the local clock) to the other (“slave”) processors. Each slave processor responds by returning a “response” time stamp (indicating the time of transmission of the response according to the local slave clock) of its own along with the received request time stamp. The master calculates clock adjustment values from the time of receipt of the responses and the included time stamps. This allows asynchronous clocks to be synchronized so that application time stamps can be validly compared across processors.Type: GrantFiled: August 8, 2003Date of Patent: March 4, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Dale C. Morris, Jonathan K. Ross
-
Patent number: 7334112Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: GrantFiled: November 6, 2003Date of Patent: February 19, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross
-
Publication number: 20080005297Abstract: A computer system comprises a physical computer and a virtual machine monitor executable on the physical computer and configured to create an emulation of at least one guest operating system adapted to control the physical computer. The computer system further comprises a host executable on the physical computer that manages physical resources coupled to the physical computer on behalf of the virtual machine monitor and the at least one guest operating system. The host is adapted to virtualize a Peripheral Component Interconnect (PCI) configuration address space whereby the at least one guest operating system controls PCI input/output (I/O) devices directly and in absence of I/O emulation.Type: ApplicationFiled: May 16, 2006Publication date: January 3, 2008Inventors: Todd J. Kjos, Jonathan K. Ross, Christophe De Dinechin
-
Patent number: 7281116Abstract: The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shootdown data, different processors can describe the memory they want to free concurrently. Thus, concurrent TLB-shootdown request are less likely to result in performance-limiting TLB-shootdown contentions that have previously constrained the scaleability of multiprocessor systems.Type: GrantFiled: July 30, 2004Date of Patent: October 9, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jonathan K. Ross, Dale Morris
-
Patent number: 7272702Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: GrantFiled: November 6, 2003Date of Patent: September 18, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross
-
Patent number: 6941449Abstract: Method and apparatus for performing a critical task using a load that is speculative. Specifically, a method of computation for performing critical tasks with speculative operations is described in one embodiment. The critical task is performed to achieve a first result while a condition of a processor used to perform said critical task is unknown. In parallel, the condition of the processor is determined. If the condition is as expected, then the first result is committed. If the condition is not as expected, then the condition is fixed to be as expected. The first result benignly fails. Also, the critical task is re-performed using the operation that is speculative resulting in a second result. The second result is then committed.Type: GrantFiled: March 4, 2002Date of Patent: September 6, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventor: Jonathan K. Ross
-
Patent number: 6931515Abstract: A method and system for determining, at run-time, whether or not to defer an exception that arises during execution of a control-speculative load instruction based on a recent history of execution of that control-speculative load instruction. The method and system relies on recent execution history stored in a speculative-load-accelerated-deferral table. If an exception arises during execution of a control-speculative load instruction, then the speculative-load-accelerated-deferral table is searched for an entry corresponding to the control-speculative load instruction. If an entry is found, then the exception is deferred, since the speculative-load-accelerated-deferral table indicates that a recent exception arising from execution of the control-speculative load instruction was not recovered via a chk.s-mediated branch to a recovery block, and not otherwise used by a non-speculative instruction.Type: GrantFiled: July 29, 2002Date of Patent: August 16, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jonathan K. Ross, Dale Morris
-
Publication number: 20040123081Abstract: A mechanism for increasing the performance of control speculation comprises executing a speculative load, returning a data value to a register targeted by the speculative load if it hits in a cache, and associating a deferral token with the speculative load if it misses in the cache. The mechanism may also issue a prefetch on a cache miss to speed execution of recovery code if the speculative load is subsequently determined to be on the control flow path.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Allan Knies, Kevin Rudd, Achmed Rumi Zahir, Dale Morris, Jonathan K. Ross
-
Publication number: 20040123083Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: ApplicationFiled: November 6, 2003Publication date: June 24, 2004Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross
-
Publication number: 20040093486Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: ApplicationFiled: November 6, 2003Publication date: May 13, 2004Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross
-
Publication number: 20040019768Abstract: A method and system for determining, at run-time, whether or not to defer an exception that arises during execution of a control-speculative load instruction based on a recent history of execution of that control-speculative load instruction. The method and system relies on recent execution history stored in a speculative-load-accelerated-deferral table. If an exception arises during execution of a control-speculative load instruction, then the speculative-load-accelerated-deferral table is searched for an entry corresponding to the control-speculative load instruction. If an entry is found, then the exception is deferred, since the speculative-load-accelerated-deferral table indicates that a recent exception arising from execution of the control-speculative load instruction was not recovered via a chk.is-mediated branch to a recovery block, and not otherwise used by a non-speculative instruction.Type: ApplicationFiled: July 29, 2002Publication date: January 29, 2004Inventors: Jonathan K. Ross, Dale Morris
-
Patent number: 6665793Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: GrantFiled: December 28, 1999Date of Patent: December 16, 2003Assignee: Institute for the Development of Emerging Architectures, L.L.C.Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross