Abstract: A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.

Abstract: A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.

Abstract: A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.

Abstract: A method of identifying defects in a chip integral to a wafer by correlating physical defects to a corresponding logic fail. The method includes partitioning a logic representation of the chip; identifying physical defects and determining corresponding coordinates of each identified physical defect; determining boundaries of the failing logic partitions, each logic partition being bound by coordinates; and correlating the physical coordinates of the defects to the bounded failing logic partitions. The scaled back, low overhead method correlates design sensitivities and test fails to physical process defects detected during semiconductor manufacturing in-line test inspection. It further identifies and records design physical coordinates of large embedded logic physical partitions test structures, memory arrays, and the like.

Abstract: A method for creating defect array paretos for semiconductor manufacturing, the method includes: merging a set of ETPLY data {the electrical overlay of bitfail map (BFM) data with inline photo inspection (PLY) data), and auto pattern recognition code (APRC) failure data to create an electrical failure data set along with a set of inline photo inspection defects that caused electrical failures; merging the APRC failure data with wafer final test (WFT) sort data to delineate array failures that are repairable from array failures that are not repairable for the calculation of kill ratios; wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes that are array failures that are not repairable; and wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes for semiconductor devices that are repairable at wafer final test.