Patents by Inventor Jonathan KLAMKIN
Jonathan KLAMKIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881490Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.Type: GrantFiled: November 2, 2022Date of Patent: January 23, 2024Assignee: Aeluma, Inc.Inventor: Jonathan Klamkin
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Patent number: 11881498Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.Type: GrantFiled: June 23, 2021Date of Patent: January 23, 2024Assignee: Aeluma, Inc.Inventor: Jonathan Klamkin
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Patent number: 11664640Abstract: A non-etched gap is introduced along the length of an integrated Bragg grating with etched grooves such that the coupling coefficient, K, of the grating is reduced by the non-etched gap. In this way, multiple grating K values may be defined within a photonic integrated circuit using a single lithography and etch step. Additionally, the non-etched gap width may be varied along the length of a single grating to implement a chirped grating.Type: GrantFiled: August 5, 2021Date of Patent: May 30, 2023Assignee: United States of America as represented by the Administrator of NASAInventors: Mark A. Stephen, Bowen Song, Jonathan Klamkin, Victoria Rosborough, Joseph Fridlander
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Patent number: 11650371Abstract: A grating coupler having first and second ends for coupling a light beam to a waveguide of a chip includes a substrate configured to receive the light beam from the first end and transmit the light beam through the second end, the substrate having a first refractive index n1, a grating structure having curved grating lines arranged on the substrate, the grating structure having a second refractive index n1, wherein the curved grating lines have line width w and height d and are arranged by a pitch ?, wherein the second refractive index n2 is less than first refractive index n1, and a cladding layer configured to cover the grating structure, wherein the cladding layer has a third refractive index n3. The curves of the grating lines are constructed such that the emitting beam is shaped for efficient coupling to another optical component. The curves can also be tilted to reduce coupling back into the waveguide.Type: GrantFiled: February 23, 2021Date of Patent: May 16, 2023Assignee: MITSUBISHI ELECTRIC RESEARCH LABORATORIES INC.Inventors: Keisuke Kojima, Satoshi Nishikawa, Shusaku Hayashi, Yosuke Suzuki, Jonathan Klamkin, Yingheng Tang
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Publication number: 20230121546Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.Type: ApplicationFiled: November 2, 2022Publication date: April 20, 2023Inventor: Jonathan KLAMKIN
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Publication number: 20230010538Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.Type: ApplicationFiled: June 23, 2021Publication date: January 12, 2023Inventor: Jonathan Klamkin
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Publication number: 20220415934Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates for vehicle applications are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.Type: ApplicationFiled: June 16, 2022Publication date: December 29, 2022Inventor: Jonathan KLAMKIN
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Publication number: 20220415950Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates for mobile applications are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.Type: ApplicationFiled: May 9, 2022Publication date: December 29, 2022Inventor: Jonathan KLAMKIN
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Publication number: 20220413156Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates for vehicle applications are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventor: Jonathan Klamkin
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Publication number: 20220413101Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates for mobile applications are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventor: Jonathan Klamkin
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Publication number: 20220415955Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventor: Jonathan Klamkin
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Patent number: 11527562Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.Type: GrantFiled: June 7, 2022Date of Patent: December 13, 2022Assignee: Aeluma, Inc.Inventor: Jonathan Klamkin
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Patent number: 11143821Abstract: An integrated grating coupler system includes a first chip having a first substrate, a first grating structure formed by first grating curves arranged on the first substrate and a cladding layer formed to cover the first grating structure, wherein the first chip include a first waveguide configured to receive a light beam from a first end via the first waveguide and transmit the light beam through a second end, a second chip having a second substrate and a second grating structure formed by second grating curves arranged on the second substrate, wherein the second chip is configured to receive the light beam from the second end of the first chip and transmit the light beam from an end of the second chip, and a common block configured to mount the first chip and second chip via a first submount and a second submount respectively, wherein the first and second submounts are arranged such that the light beam from the second end of the first chip is received at a top of the second chip.Type: GrantFiled: March 24, 2020Date of Patent: October 12, 2021Assignees: Mitsubishi Electric Research Laboratories, Inc., Mitsubishi Electric CorporationInventors: Keisuke Kojima, Satoshi Nishikawa, Jonathan Klamkin
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Patent number: 11079550Abstract: A grating coupler having first and second ends for coupling a light beam to a waveguide of a chip includes a substrate configured to receive the light beam from the first end and transmit the light beam through the second end, the substrate having a first refractive index n1, a grating structure having curved grating lines arranged on the substrate, the grating structure having a second refractive index n1, wherein the curved grating lines have line width w and height d and are arranged by a pitch ?, wherein the second refractive index n2 is less than first refractive index n1, and a cladding layer configured to cover the grating structure, wherein the cladding layer has a third refractive index n3. The curves of the grating lines are constructed such that the emitting beam is shaped for efficient coupling to another optical component. The curves can also be tilted to reduce coupling back into the waveguide.Type: GrantFiled: January 28, 2020Date of Patent: August 3, 2021Assignee: Mitsubishi Electric Research Laboratories, Inc.Inventors: Keisuke Kojima, Satoshi Nishikawa, Shusaku Hayashi, Yosuke Suzuki, Jonathan Klamkin, Yingheng Tang
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Publication number: 20210181427Abstract: A grating coupler having first and second ends for coupling a light beam to a waveguide of a chip includes a substrate configured to receive the light beam from the first end and transmit the light beam through the second end, the substrate having a first refractive index n1, a grating structure having curved grating lines arranged on the substrate, the grating structure having a second refractive index n1, wherein the curved grating lines have line width w and height d and are arranged by a pitch ?, wherein the second refractive index n2 is less than first refractive index n1, and a cladding layer configured to cover the grating structure, wherein the cladding layer has a third refractive index n3. The curves of the grating lines are constructed such that the emitting beam is shaped for efficient coupling to another optical component. The curves can also be tilted to reduce coupling back into the waveguide.Type: ApplicationFiled: February 23, 2021Publication date: June 17, 2021Applicants: Mitsubishi Electric Research Laboratories, Inc., Mitsubishi Electric CorporationInventors: Keisuke Kojima, Satoshi Nishikawa, Shusaku Hayashi, Yosuke Suzuki, Jonathan Klamkin, Yingheng Tang
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Patent number: 11029466Abstract: There is set forth herein a method including a substrate; a dielectric stack disposed on the substrate; one or more photonics device integrated in the dielectric stack; and a laser light source having a laser stack including a plurality of structures arranged in a stack, wherein structures of the plurality of structures are integrated in the dielectric stack, wherein the laser stack includes an active region configured to emit light in response to the application of electrical energy to the laser stack.Type: GrantFiled: September 19, 2019Date of Patent: June 8, 2021Assignees: The Research Foundation for the State University of New York, The Regents of the University of CaliforniaInventors: William Charles, John Bowers, Douglas Coolbaugh, Daehwan Jung, Jonathan Klamkin, Douglas La Tulipe, Gerald L. Leake, Jr., Songtao Liu, Justin Norman
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Publication number: 20210116645Abstract: A grating coupler having first and second ends for coupling a light beam to a waveguide of a chip includes a substrate configured to receive the light beam from the first end and transmit the light beam through the second end, the substrate having a first refractive index n1, a grating structure having curved grating lines arranged on the substrate, the grating structure having a second refractive index n1, wherein the curved grating lines have line width w and height d and are arranged by a pitch ?, wherein the second refractive index n2 is less than first refractive index n1, and a cladding layer configured to cover the grating structure, wherein the cladding layer has a third refractive index n3. The curves of the grating lines are constructed such that the emitting beam is shaped for efficient coupling to another optical component. The curves can also be tilted to reduce coupling back into the waveguide.Type: ApplicationFiled: January 28, 2020Publication date: April 22, 2021Applicants: Mitsubishi Electric Research Laboratories, Inc., Mitsubishi Electric CorporationInventors: Keisuke Kojima, Satoshi Nishikawa, Shusaku Hayashi, Yosuke Suzuki, Jonathan Klamkin, Yingheng Tang
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Publication number: 20200166703Abstract: There is set forth herein a method including a substrate; a dielectric stack disposed on the substrate; one or more photonics device integrated in the dielectric stack; and a laser light source having a laser stack including a plurality of structures arranged in a stack, wherein structures of the plurality of structures are integrated in the dielectric stack, wherein the laser stack includes an active region configured to emit light in response to the application of electrical energy to the laser stack.Type: ApplicationFiled: September 19, 2019Publication date: May 28, 2020Inventors: William CHARLES, John BOWERS, Douglas COOLBAUGH, Daehwan JUNG, Jonathan KLAMKIN, Douglas La Tulipe, Gerald L. LEAKE, JR., Songtao LIU, Justin NORMAN
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Publication number: 20180081118Abstract: Two or more monolithic or heterogeneously integrated substrates are attached to each other and optically edge-coupled using spot-size converters. Spot-size converters are placed between planar optical waveguides and cleaved or etched facets in each substrate. The facets are provide optical edge coupling and the spot-size converters are used to adjust at least the size, shape, and divergence of the optical beams entering or exiting the optical waveguides as to improve the optical coupling between the substrates. In addition to spot-size converters, filtering and other light adjusting elements may be placed between the substrates. Integrated lasers, semiconductor optical amplifiers, and photonic integrated circuits can be provided with complementary metal-oxide semiconductor (CMOS)-compatible silicon (Si) photonic substrates, which can also contain integrated electronics.Type: ApplicationFiled: May 1, 2017Publication date: March 22, 2018Applicant: Biond Photonics Inc.Inventors: Jonathan Klamkin, Sasa Ristic
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Publication number: 20170207600Abstract: Methods for realizing integrated lasers and photonic integrated circuits on complimentary metal-oxide semiconductor (CMOS)-compatible silicon (Si) photonic chips, potentially containing integrated electronics, are disclosed. The integration techniques rely on light coupling with integrated light coupling elements such as turning mirrors, lenses, and surface grating couplers. Light is coupled from between two or more substrates using the light coupling elements. The technique can realize integrated lasers on Si where a gain flip chip (the second substrate) is bonded to a Si chip (the first substrate) and light is coupled between a waveguide in the gain flip chip to a Si waveguide by way of a turning mirror or grating coupler in the flip chip and a grating coupler in the Si chip. Integrated lenses and other elements such as spot-size converters can also be incorporated to alter the mode from the gain flip chip to enhance the coupling efficiency to the Si chip.Type: ApplicationFiled: July 14, 2015Publication date: July 20, 2017Applicant: Biond Photonics Inc.Inventors: Jonathan Klamkin, Sasa Ristic