Abstract: A method and device for a sensor using a selectively transparent buffer material. The method includes forming a buffer region overlying a silicon substrate, and forming a wavelength configuring material overlying the buffer region. This wavelength configuring material can be configured for non-absorption of a selected wavelength range via plurality of material regions having at least alternating first and second material compositions. The material compositions can include InP, InGaAs, GaAs, GaP, InGaAsP, InAs, InAlAs, InAlGaAs, InGaP, or the like. These materials can also include strained layer superlattice (SLS) or strained interlayer (SIL) materials as dislocation filter layers. Device materials; including at least an n-type contact region, an absorption region, one or more band transition region, a p-type spacer region, and a p-type contact region; can be formed overlying the wavelength configuring material.

Abstract: An integrated sensor array device and method. The method includes providing a partially completed semiconductor substrate having a material stack used to form a sensor array device with a plurality of device regions. One or more isolation trench regions separating the device regions can be formed in a front-end isolation process during the formation of the device regions or in a back-end isolation process following a bonding process to integrate the sensor array device to an integrated circuit (IC) device. Prior to the front-end or back-end processing, metal interconnect materials within a passivation material can be formed via a planarization process to provide connection to n-type and p-type contact regions of the sensor array device. The resulting planarized sensor array device can then be bonded to the IC device, and a plurality of surface relief structures can be formed overlying a backside surface region of the planarized sensor array device.

Abstract: A stacked focal planar array (FPA) device and method of fabrication. The method can include forming photodetectors or FPAs by heteroepitaxial growth of III-V PINs, APDs, or other photodetector devices that are bonded to a Si-based read-out integrated circuit (ROIC) wafer in a stacked configuration. In a single-color device example, a wavelength configuring buffer layer and photodetector are grown on a first substrate using compound semiconductor materials to enable infrared detection at desired wavelength(s). Depending on the application, this growth can be done on a graded compliant buffer layer and/or a selectively transparent buffer layer. And, silicon detectors can be incorporated to detect visible and NIR wavelengths in a dual-color device example. Further, the resulting devices can be bonded overlying the ROIC device in a flipped orientation and configured as pixels in a sensor array device coupled to the ROIC device.

Abstract: A method and device for a sensor using a graded wavelength configuring material. The wavelength configuring material can be configured for a selected wavelength using plurality of material regions of varying elemental concentrations in a continuous or step-wise pattern. The material compositions can include InP, InGaAs, GaAs, GaP, InGaAsP, InAs, InAlAs, InAlGaAs, InGaP, and the like. Further, the interface regions between adjacent material regions can be free from smearing of compositions. These material regions can also form a strained graded region overlying a buffer material and a silicon substrate. An array of photodetector materials can be formed overlying the wavelength configuring material. These materials can include an n-type material, an absorption material, a band transition material, and a p-type material, among others. The resulting device exhibits high performance at the selected wavelength and is characterized by low dislocation density.

Abstract: A method and device for a photodetector circuit using a near infrared (NIR) compliant substrate. The substrate includes a plurality of v-grooves formed within a front region and at least a first GaAs buffer region, a defect filter layer (DFL), and a second GaAs buffer region formed overlying. The device can also include an overlying wavelength configuring material having a graded region with a plurality of material regions configured in order of concentration with respect to at least a first element concentration, which can be configured for a selected wavelength. Then, photodetector device materials can be formed overlying the wavelength configuring material and can include at least an n-type contact region, an absorber region, a p-type spacer region, and a p-type contact region. These device materials can be configured in an array of photomultiplier (PM) devices, single photon avalanche detector (SPAD) devices, or the like.

Abstract: A sensor device and method of fabrication therefor. The method includes providing a partially completed semiconductor substrate having the following stacked materials: a silicon substrate, a buffer material, an n-type semiconductor material, an unintentionally doped (UID) optically absorptive material, a UID optically transparent semiconductor material, and a native insulating material. The substrate is sealed in a predetermined environment within a first carrier device, and then transferred from a first geographic location to a second geographic location. The substrate is then transferred to a second carrier device and cleaned. A dielectric material is formed overlying the substrate and patterned to form a p-type contact region and an n-type contact region. A p-type semiconductor region is formed via the p-type contact region, a p-type metal contact is formed overlying the p-type contact region, and an n-type metal contact is formed overlying the n-type contact region to form a common n-type electrode.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates for mobile applications are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: A method and device for a photodetector circuit using a near infrared (NIR) compliant substrate. The substrate includes a plurality of v-grooves formed within a front region and at least a first GaAs buffer region, a defect filter layer (DFL), and a second GaAs buffer region formed overlying. The device can also include an overlying wavelength configuring material having a graded region with a plurality of material regions configured in order of concentration with respect to at least a first element concentration, which can be configured for a selected wavelength. Then, photodetector device materials can be formed overlying the wavelength configuring material and can include at least an n-type contact region, an absorber region, a p-type spacer region, and a p-type contact region. These device materials can be configured in an array of photomultiplier (PM) devices, single photon avalanche detector (SPAD) devices, or the like.

Abstract: A method and device for a sensor using a graded wavelength configuring material. The wavelength configuring material can be configured for a selected wavelength using plurality of material regions of varying elemental concentrations in a continuous or step-wise pattern. The material compositions can include InP, InGaAs, GaAs, GaP, InGaAsP, InAs, InAlAs, InAlGaAs, InGaP, and the like. Further, the interface regions between adjacent material regions can be free from smearing of compositions. These material regions can also form a strained graded region overlying a buffer material and a silicon substrate. An array of photodetector materials can be formed overlying the wavelength configuring material. These materials can include an n-type material, an absorption material, a band transition material, and a p-type material, among others. The resulting device exhibits high performance at the selected wavelength and is characterized by low dislocation density.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates for vehicle applications are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates for vehicle applications are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: A stacked focal planar array (FPA) device and method of fabrication. The method can include forming photodetectors or FPAs by heteroepitaxial growth of III-V PINS, APDs, or other photodetector devices that are bonded to a Si-based read-out integrated circuit (ROIC) wafer in a stacked configuration. In a single-color device example, a wavelength configuring buffer layer and photodetector are grown on a first substrate using compound semiconductor materials to enable infrared detection at desired wavelength(s). Depending on the application, this growth can be done on a graded compliant buffer layer and/or a selectively transparent buffer layer. And, silicon detectors can be incorporated to detect visible and NIR wavelengths in a dual-color device example. Further, the resulting devices can be bonded overlying the ROIC device in a flipped orientation and configured as pixels in a sensor array device coupled to the ROIC device.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates for mobile applications are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: A non-etched gap is introduced along the length of an integrated Bragg grating with etched grooves such that the coupling coefficient, K, of the grating is reduced by the non-etched gap. In this way, multiple grating K values may be defined within a photonic integrated circuit using a single lithography and etch step. Additionally, the non-etched gap width may be varied along the length of a single grating to implement a chirped grating.