Patents by Inventor Jonathan Kuppinger

Jonathan Kuppinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060136855
    Abstract: A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Inventors: Jason Hoff, Viswanathan Lakshmanan, Michael Josephides, Daniel Prevedel, Richard Blinne, Jonathan Kuppinger
  • Publication number: 20060064656
    Abstract: A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.
    Type: Application
    Filed: September 22, 2004
    Publication date: March 23, 2006
    Inventors: Viswanathan Lakshmanan, Alan Holesovsky, Lisa Miller, Jonathan Kuppinger
  • Publication number: 20050235234
    Abstract: A method and computer program product for verifying an incremental change to an integrated circuit design are described that include steps of: (a) receiving as input an integrated circuit design database; (b) receiving as input an engineering change order; (c) identifying and marking objects in the integrated circuit design database to indicate a current state of the integrated circuit design database; (d) applying the engineering change order to the integrated circuit design database; (e) analyzing the integrated circuit design database to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order; (f) identifying and marking objects in the integrated circuit design database included in the list of incremental changes to distinguish objects in the integrated circuit design database that were changed from the current state; and (g) streaming out the integrated circuit design database.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 20, 2005
    Inventors: Viswanathan Lakshmanan, Richard Blinne, Jonathan Kuppinger
  • Publication number: 20050097488
    Abstract: A method of partitioning an integrated circuit design for physical design verification includes steps of: (a) receiving as input a representation of an integrated circuit design having a number of physical design layers; (b) receiving as input a composite run deck specifying rule checks to be performed on the integrated circuit design; (c) partitioning the composite run deck into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum; (d) parsing the representation of the integrated circuit design to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks; and (e) generating as output the filtered data deck for each of the partitioned run decks.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 5, 2005
    Inventors: Viswanathan Lakshmanan, Richard Blinne, Jonathan Kuppinger