Patents by Inventor Jonathan L. Cobb

Jonathan L. Cobb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cr-capped chromeless phase lithography
    Patent number: 7732102
    Abstract: A photolithographic mask is adapted for use in imparting a pattern to a substrate. The pattern comprises a plurality of features. At least one of the plurality of features (201) is implemented in the mask as a phase shifting structure (205) with a unitary layer of opaque material (207) disposed thereon. The mask is utilized to impart the pattern to a layer over a semiconductor substrate.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: June 8, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan L. Cobb, Bernard J. Roman, Wei E. Wu
  • Treatment for reduction of line edge roughness
    Patent number: 7670760
    Abstract: A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: March 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinmiao James Shen, Jonathan L. Cobb, William D. Darlington, Brian J. Fisher, Mark D. Hall, Vikas R. Sheth, Mehul D. Shroff, James E. Vasek
  • Non-resolving mask tiling method for flare reduction
    Patent number: 6989229
    Abstract: Photoresist on a wafer is exposed using tiles on a mask that improve flare performance. Features that are not to be exposed on the photoresist correspond to features on the mask. The various features are surrounded by other features that vary and thus affect flare differently. Selected features have tiles added nearby but also far enough away to improve uniformity in the effects of flare on the various features that are intended to be present in the photoresist. The tiles are made either very small in width or partially absorbing so that the tiles are not resolved in the photoresist. Thus the tiles reduce flare but do not alter the desired pattern in the photoresist.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: January 24, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kevin D. Lucas, Jonathan L. Cobb, William L. Wilkinson
  • Non-resolving mask tiling method for flare reduction
    Publication number: 20040188383
    Abstract: Photoresist on a wafer is exposed using tiles on a mask that improve flare performance. Features that are not to be exposed on the photoresist correspond to features on the mask. The various features are surrounded by other features that vary and thus affect flare differently. Selected features have tiles added nearby but also far enough away to improve uniformity in the effects of flare on the various features that are intended to be present in the photoresist. The tiles are made either very small in width or partially absorbing so that the tiles are not resolved in the photoresist. Thus the tiles reduce flare but do not alter the desired pattern in the photoresist.
    Type: Application
    Filed: March 27, 2003
    Publication date: September 30, 2004
    Inventors: Kevin D. Lucas, Jonathan L. Cobb, William L. Wilkinson