Abstract: A method, computer program product, and computer system for consolidating, at a computing device, a number of parallel streams, entering a hardware accelerator in a cluster, into fewer streams. The fewer streams, exiting the hardware accelerator in the cluster, may be returned back into the number of parallel streams.

Abstract: For a chassis having a port mounted on a side of the chassis and connected to electronics in the chassis, with a plug mated in the port and a cable connected to the plug, first and second supports are mounted on the chassis side on opposing sides of the port, where each support has a respective, predetermined length extending away from the chassis side. A strap defines a slot beginning at a first end of the strap and extending along a portion of the strap's length. The strap is placed with the cable inserted in the slot and the plug at a central portion of the strap. With the supports mounted on the chassis side on opposing sides of the port, the strap connected to the respective supports, at least the plug forces curvature in a central portion of the strap, so that the central portion of the strap clamps the plug.

Abstract: For a chassis having a port mounted on a side of the chassis and connected to electronics in the chassis, with a plug mated in the port and a cable connected to the plug, first and second supports are mounted on the chassis side on opposing sides of the port, where each support has a respective, predetermined length extending away from the chassis side. A strap defines a slot beginning at a first end of the strap and extending along a portion of the strap's length. The strap is placed with the cable inserted in the slot and the plug at a central portion of the strap. With the supports mounted on the chassis side on opposing sides of the port, the strap connected to the respective supports, at least the plug forces curvature in a central portion of the strap, so that the central portion of the strap clamps the plug.

Abstract: For a chassis having a port mounted on a side of the chassis and connected to electronics in the chassis, with a plug mated in the port and a cable connected to the plug, first and second supports are mounted on the chassis side on opposing sides of the port, where each support has a respective, predetermined length extending away from the chassis side. A strap defines a slot beginning at a first end of the strap and extending along a portion of the strap's length. The strap is placed with the cable inserted in the slot and the plug at a central portion of the strap. With the supports mounted on the chassis side on opposing sides of the port, the strap connected to the respective supports, at least the plug forces curvature in a central portion of the strap, so that the central portion of the strap clamps the plug.

Abstract: A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.

Abstract: A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.

Abstract: A management controller in a distributed network switch may operate on sets of ports such that sets of ports containing a same port are processed serially, and sets that do not contain any of the same ports can be processed in parallel. When receiving a set of ports for processing, the management controller organizes the ports into lanes that each correspond to a unique port. If any of the lanes overlap, subsequent port sets are blocked from proceeding until the lanes of preceding port sets are cleared. If no lanes overlap, the sets may be deemed disjoint, and subsequent port sets may be processed in parallel.

Abstract: A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.

Abstract: A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.

Abstract: A management controller in a distributed network switch may operate on sets of ports such that sets of ports containing a same port are processed serially, and sets that do not contain any of the same ports can be processed in parallel. When receiving a set of ports for processing, the management controller organizes the ports into lanes that each correspond to a unique port. If any of the lanes overlap, subsequent port sets are blocked from proceeding until the lanes of preceding port sets are cleared. If no lanes overlap, the sets may be deemed disjoint, and subsequent port sets may be processed in parallel.

Abstract: Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports.

Abstract: Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports.

Abstract: Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports.

Abstract: Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports.

Abstract: In an embodiment, a power off command is received that specifies a slot in a computer that connects to a first adapter. The first adapter comprises a physical and virtual functions. Data transfer from a logical partition to the virtual function is stopped, a lock of the virtual function held by the logical partition is released, and the slot is powered off. Ownership of the virtual function is retained by the logical partition while the lock is released and the slot is powered off. A power on command is received that specifies the slot that connects to a second adapter. The second adapter comprises the physical and virtual functions. In response to the power on command, the slot is powered on, and the lock is obtained of the virtual function for the logical partition.

Abstract: A hypervisor-based facility is provided for communicating between a hardware management console (HMC) and a logical partition of a data processing system. The facility includes: packaging a request or response of a source endpoint as cargo in a generic transport primitive, the source endpoint being either an HMC or a logical partition of the data processing system; and forwarding the generic transport primitive from the source endpoint to a target endpoint via the hypervisor. The forwarding includes receiving the transport primitive at the hypervisor and forwarding the cargo of the transport primitive to the target endpoint. The cargo includes the request or response from the source endpoint, and the hypervisor forwards the cargo absent inspection or parsing of that cargo. The target endpoint is the other one of the logical partition or the hardware management console of the data processing system.

Abstract: In an embodiment, a power off command is received that specifies a slot in a computer that connects to a first adapter. The first adapter comprises a physical and virtual functions. Data transfer from a logical partition to the virtual function is stopped, a lock of the virtual function held by the logical partition is released, and the slot is powered off. Ownership of the virtual function is retained by the logical partition while the lock is released and the slot is powered off. A power on command is received that specifies the slot that connects to a second adapter. The second adapter comprises the physical and virtual functions. In response to the power on command, the slot is powered on, and the lock is obtained of the virtual function for the logical partition.

Abstract: A hypervisor-based facility is provided for communicating between a hardware management console (HMC) and a logical partition of a data processing system. The facility includes: packaging a request or response of a source endpoint as cargo in a generic transport primitive, the source endpoint being either an HMC or a logical partition of the data processing system; and forwarding the generic transport primitive from the source endpoint to a target endpoint via the hypervisor. The forwarding includes receiving the transport primitive at the hypervisor and forwarding the cargo of the transport primitive to the target endpoint. The cargo includes the request or response from the source endpoint, and the hypervisor forwards the cargo absent inspection or parsing of that cargo. The target endpoint is the other one of the logical partition or the hardware management console of the data processing system.