Abstract: The present disclosure generally relates to semiconductor processing for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a multi-depth isolation structure in the semiconductor substrate, and a BJT on the semiconductor substrate. The multi-depth isolation structure includes a first isolation portion in the semiconductor substrate and a second isolation portion in the semiconductor substrate. The first isolation portion is to a first depth in the semiconductor substrate. The second isolation portion is to a second depth in the semiconductor substrate. The first depth is deeper in the semiconductor substrate than the second depth. The BJT includes a collector region and a base layer. The collector region is in the semiconductor substrate laterally between the first isolation portion and the second isolation portion. The base layer is on the collector region and over and adjoining the first isolation portion and the second isolation portion.

Abstract: The invention provides methods of preparing 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid and methods of making a pharmaceutical material comprising a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid. Also provided are compositions and pharmaceutical materials including a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid as well as methods of treating various diseases and conditions using the compositions and pharmaceutical materials.

Abstract: In examples, a device includes a semiconductor substrate, a pedestal dielectric stack, a bipolar junction transistor (BJT), a field effect transistor (FET), and a composite structure. The substrate includes a BJT region, a FET region, and a transition region between the BJT and FET regions. The BJT and FET are on the substrate in the BJT and FET regions, respectively. A BJT portion is in an opening through the pedestal dielectric stack. The opening is defined at least in part by a retrograde sidewall. The composite structure is on the substrate in the transition region and includes a residual dielectric stack, a dielectric layer over the residual dielectric stack, and a first material over the dielectric layer. The residual dielectric stack has a material same as the pedestal dielectric stack. The dielectric layer includes a nitride. The first material is same as a gate electrode of the FET.

Abstract: The present disclosure generally relates to semiconductor processing including facet trapping for an epitaxial growth process. In an example, a dielectric layer is formed over a first semiconductor material that includes a monocrystalline surface. A recess is formed in the dielectric layer and is defined by a recess sidewall. A spacer layer is formed conformally in the recess. A sidewall spacer is formed from the spacer layer and is along the recess sidewall. An opening is formed through the dielectric layer to the monocrystalline surface. Forming the opening includes etching the dielectric layer under the sidewall spacer. The opening is defined by an opening sidewall corresponding to the recess sidewall and a cavity in the dielectric layer. The cavity is at the monocrystalline surface and under the opening sidewall. A second semiconductor material is formed on the monocrystalline surface and in the opening.

Abstract: Disclosed herein are methods of manufacturing pyridazinone compounds useful in the treatment of Duchenne Muscular Dystrophy using Suzuki cross-coupling reactions.

Abstract: The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a bipolar junction transistor (BJT), a field effect transistor (FET), and a composite structure. The semiconductor substrate includes a BJT region, a complementary FET (CFET) region, and a transition region between the BJT region and the CFET region. The BJT is on the semiconductor substrate in the BJT region. The FET is on the semiconductor substrate in the CFET region. The composite structure is on the semiconductor substrate in the transition region. The composite structure includes a dielectric material. The dielectric material has a sidewall proximate and facing the CFET region and has a top surface that forms at least a portion of an upper surface of the composite structure.

Abstract: The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, an etch stop layer, a pedestal dielectric layer, a BJT, and a field effect transistor (FET). The semiconductor substrate includes a BJT region and a complementary FET (CFET) region. The etch stop layer is over the semiconductor substrate in the BJT region. The pedestal dielectric layer is over the etch stop layer in the BJT region. The BJT is on the semiconductor substrate in the BJT region. At least a first portion of the BJT is in an opening through the pedestal dielectric layer and the etch stop layer. At least a second portion of the BJT is further over the pedestal dielectric layer. The FET is on the semiconductor substrate in the CFET region.

Abstract: The present disclosure generally relates to semiconductor processing for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate and a bipolar junction transistor on the semiconductor substrate. The bipolar junction transistor includes a collector layer on the semiconductor substrate, a base layer on the collector layer, a raised base layer on the base layer, a dielectric spacer on the base layer and along a sidewall of the raised base layer, and an emitter layer on the base layer. The dielectric spacer is laterally between the raised base layer and the emitter layer. The emitter layer extends over the dielectric spacer and at least partially over the raised base layer. The raised base layer has a substantially continuous upper surface from a distance away from the emitter layer to the dielectric spacer underlying the emitter layer.

Abstract: The invention provides methods of preparing 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid and methods of making a pharmaceutical material comprising a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid. Also provided are compositions and pharmaceutical materials including a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid as well as methods of treating various diseases and conditions using the compositions and pharmaceutical materials.

Abstract: The present invention relates to animal food, in particular pet food comprising a combination of spray-dried plasma and fructo-oligosaccharides. The invention further relates to the use of such compositions for improving gastro-intestinal digestion, gut microbial diversity and fermentation, nutrient absorption, and/or immunity in an animal.

Abstract: The invention provides methods of preparing 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid and methods of making a pharmaceutical material comprising a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid. Also provided are compositions and pharmaceutical materials including a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid as well as methods of treating various diseases and conditions using the compositions and pharmaceutical materials.

Abstract: The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a BJT, a field effect transistor (FET), and a composite structure. The semiconductor substrate includes a BJT region, a complementary FET (CFET) region, and a transition region between the BJT region and the CFET region. The BJT is on the semiconductor substrate in the BJT region. The FET is on the semiconductor substrate in the CFET region. The composite structure is on the semiconductor substrate in the transition region. The composite structure includes a material that is the same as a gate electrode of the FET.

Abstract: The present disclosure generally relates to an integrated circuit (IC) including a flash memory bit structure. In an example, an IC includes a flash memory bit structure and a transistor structure. The flash memory bit structure is on a semiconductor substrate. The flash memory bit structure includes a word line structure and a first oxide layer disposed between the semiconductor substrate and the word line structure. The first oxide layer is free of nitridation. The transistor structure is on the semiconductor substrate. The transistor structure includes a gate structure and a gate oxide layer including nitridation. The gate oxide layer is over the semiconductor substrate. The gate structure is over the gate oxide layer.

Abstract: The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a pedestal dielectric layer, a collector layer, a base layer, and an emitter layer. The semiconductor substrate includes a bipolar junction transistor region. The pedestal dielectric layer is in the bipolar junction transistor region and is over an upper surface of the semiconductor substrate. The collector layer is on the upper surface of the semiconductor substrate and is through the pedestal dielectric layer. The base layer is on the collector layer and an upper surface of the pedestal dielectric layer. The pedestal dielectric layer extends laterally over the upper surface of the semiconductor substrate from the base layer. The emitter layer is on the base layer.

Abstract: An integrated circuit (IC) including Flash memory and CMOS logic circuitry and a method of fabrication thereof is disclosed. The IC comprises a substrate including a first region and a second region, where a Flash memory cell gate stack is formed in the first region, a first transistor is formed in the first region and operable at a first voltage level, the first transistor including a gate formed over a first gate oxide layer exclusive of nitridation, and one or more sets of second transistors are formed in the second region, each set operable at a corresponding second voltage level different than the first voltage level and including a corresponding second gate oxide layer having nitridation.

Abstract: An integrated circuit (IC) including Flash memory and CMOS logic circuitry and a method of fabrication thereof is disclosed. The IC comprises a substrate including a recessed area of a first region, a Flash memory cell gate stack formed in the recessed area, a wordline (WL) transistor formed in the recessed area and coupled with the Flash memory cell gate stack, the WL transistor including a WL gate formed over a first gate oxide layer exclusive of nitridation, and a transistor formed in a second area of the substrate separate from the recessed area, the transistor forming at least a portion of logic circuitry of the IC and including a second gate oxide layer having nitridation.

Abstract: The invention provides methods of preparing 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid and methods of making a pharmaceutical material comprising a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid. Also provided are compositions and pharmaceutical materials including a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid as well as methods of treating various diseases and conditions using the compositions and pharmaceutical materials.

Abstract: The invention provides methods of preparing 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid and methods of making a pharmaceutical material comprising a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid. Also provided are compositions and pharmaceutical materials including a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid as well as methods of treating various diseases and conditions using the compositions and pharmaceutical materials.

Abstract: The invention provides methods of preparing 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid and methods of making a pharmaceutical material comprising a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid. Also provided are compositions and pharmaceutical materials including a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid as well as methods of treating various diseases and conditions using the compositions and pharmaceutical materials.

Abstract: The invention provides methods of preparing 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid and methods of making a pharmaceutical material comprising a purified amount of 8-hydroxy-2,2,14, 14-tetramethylpentadecanedioic acid. Also provided are compositions and pharmaceutical materials including a purified amount of 8-hydroxy-2,2,14,14-tetramethylpentadecanedioic acid as well as methods of treating various diseases and conditions using the compositions and pharmaceutical materials.