Abstract: A transistor circuit includes a main transistor having a gate terminal, a drain terminal and a source terminal, and a drain lag compensation circuit configured to sense a drain voltage on the drain terminal of the main transistor and to control a drain current through the main transistor based on the sensed drain voltage. The drain lag compensation circuit may include a reference transistor having a drain terminal coupled to a drain terminal of the main transistor, and a sensing circuit that is coupled to a source terminal of the reference transistor and provides a control voltage to a gate terminal of the main transistor. The reference transistor may be thermally coupled to the main transistor. The main transistor may be a GaN RF power transistor.

Abstract: An apparatus having an active device, a plurality of traces and one or more areas is disclosed. The active device may have a channel layer. A buffer layer is generally disposed between the channel layer and a substrate. A parasitic layer may be formed at an interface between the buffer layer and the substrate. The traces may be connected to the active device. The areas are generally proximate at least one of (i) the active device and (ii) at least two of the traces from which the parasitic layer is removed.