Patents by Inventor Jonathan Lee RULLAN

Jonathan Lee RULLAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES
    Publication number: 20170047248
    Abstract: A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.
    Type: Application
    Filed: November 1, 2016
    Publication date: February 16, 2017
    Inventors: Jonathan Lee RULLAN, Sunil Kumar SINGH
  • Filling cavities in an integrated circuit and resulting devices
    Patent number: 9524935
    Abstract: A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jonathan Lee Rullan, Sunil Kumar Singh
  • FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES
    Publication number: 20160336264
    Abstract: A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.
    Type: Application
    Filed: May 13, 2015
    Publication date: November 17, 2016
    Inventors: Jonathan Lee RULLAN, Sunil Kumar SINGH