Patents by Inventor Jonathan Longrigg

Jonathan Longrigg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Optimizing place-and-routing using a random normalized polish expression
    Patent number: 12032893
    Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: July 9, 2024
    Assignee: Pulsic Limited
    Inventors: Mark Waller, Paul Clewes, Liang Gao, Jonathan Longrigg
  • Automated analog layout
    Patent number: 11748538
    Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: September 5, 2023
    Assignee: Pulsic Limited
    Inventors: Paul Clewes, Liang Gao, Jonathan Longrigg
  • Optimizing Place-and-Routing Using a Random Normalized Polish Expression
    Publication number: 20220108059
    Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.
    Type: Application
    Filed: December 14, 2021
    Publication date: April 7, 2022
    Inventors: Mark Waller, Paul Clewes, Liang Gao, Jonathan Longrigg
  • Automated analog layout
    Patent number: 11281828
    Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 22, 2022
    Assignee: Pulsic Limited
    Inventors: Paul Clewes, Liang Gao, Jonathan Longrigg
  • Optimizing place-and-routing using a random normalized polish expression
    Patent number: 11200363
    Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: December 14, 2021
    Assignee: Pulsic Limited
    Inventors: Mark Waller, Paul Clewes, Liang Gao, Jonathan Longrigg
  • Automated analog layout
    Patent number: 10783292
    Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: September 22, 2020
    Assignee: Pulsic Limited
    Inventors: Paul Clewes, Liang Gao, Jonathan Longrigg
  • Method for optimizing place-and-routing using a random normalized polish expression
    Patent number: 10726184
    Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: July 28, 2020
    Assignee: Pulsic Limited
    Inventors: Mark Waller, Paul Clewes, Liang Gao, Jonathan Longrigg
  • Method for optimizing place-and-routing using a random normalized polish expression
    Patent number: 9940421
    Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on a random normalized polish expression, and includes cost considerations based on routing of interconnect.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: April 10, 2018
    Assignee: Pulsic Limited
    Inventors: Mark Waller, Paul Clewes, Liang Gao, Jonathan Longrigg