Abstract: A quantum computing system including a quantum computing resource having a plurality of logical qubits, a classical memory, an on-chip decoder controller, and at least one classical processor is disclosed. The on-chip decoder controller (i) measures, during a respective cycle, a plurality of parity ancilla qubits corresponding to a plurality of physical data qubits of a logical qubit; (ii) in accordance with the measured plurality of parity ancilla qubits, generates a plurality of error signatures corresponding to the plurality of physical data qubits; (iii) categorizes each error signature of the plurality of error signatures into a simple error signature or a complex error signature; (iv) applies error correction to at least one physical data qubit of the plurality of physical data qubits corresponding to each simple error signature; and (v) transfers each complex error signature for off-chip decoding by the at least one classical processor.

Abstract: A host computer includes a processor, a first memory for storing a bit map representation of an image to be printed, and a second memory for storing a control language representation of an image to be printed. The host computer further includes a printer driver for enabling dispatch of the bit map representation to a connected printer. The printer includes a print engine, a printer processor and control memory for storing bit map control code which controls the printer processor to render the print engine able to print an image defined by a bit map representation. The control memory further includes control language code for controlling the printer's processor to render the print engine able to print an image defined by a control language representation. Within the host computer is an interface module, controlled by the host printer driver, for interrogating status information from the printer.