Abstract: A circuit design technique is provided for automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout. The automatically estimating includes automatically generating pin locations for a plurality of pins in at least one level of the hierarchy to be employed with the at least some circuit components of the circuit layout, wherein the interconnect segments interconnect the plurality of pins. A route estimator is employed to estimate lengths of the interconnect segments based on the pin locations of the plurality of pins. The estimated interconnect segment lengths are then employed in automatically estimating resistance capacitance interconnect parasitics for the interconnect segments to be employed in the circuit layout.