Abstract: The invention provides a system for creating a prescribed vibration profile on a mechanical device comprising a sensor for measuring an operating condition of the mechanical device, a circular force generator for creating a controllable rotating force vector comprising a controllable force magnitude, a controllable force phase and a controllable force frequency, a controller in electronic communication with said sensor and said circular force generator, the controller operably controlling the controllable rotating force vector, wherein the difference between the measured operating condition and a desired operating condition is minimized.

Abstract: An isolator (200) has an outer housing (224) comprising an outer housing bore (234), an inner member (240) received coaxially within the outer housing (224), a precompressed compression compliance component (CCC) (230) disposed between the outer housing (224) and the inner member (240), the CCC (230) being configured to bias the inner member (240) in an axial direction, and a precompressed rebound compliance component (RCC) (232) disposed between the outer housing (224) and the inner member (240), the RCC (232) being configured to bias the inner member (240) in an opposite axial direction.

Abstract: A method of controlling the vibration of a vibratory separator, the method including providing a vibratory separator having a frame and a plurality of force generators coupled to the frame and a control unit operatively connected to each of the plurality of force generators, and independently controlling each of the plurality of force generators. Independently controlling each of the plurality of force generators controls a motion profile of the vibratory separator.

Abstract: A method of controlling the vibration of a vibratory separator, the method including providing a vibratory separator having a frame and a plurality of force generators coupled to the frame and a control unit operatively connected to each of the plurality of force generators, and independently controlling each of the plurality of force generators. Independently controlling each of the plurality of force generators controls a motion profile of the vibratory separator.

Abstract: A coupling suitable for transmitting torque applied to a first input to a second input shaft wherein the coupling accommodates angular changes between the input shafts. Additionally, the disclosure describes an improved mud motor transmission incorporating the coupling.

Abstract: A data-logging truck control system controls magnetorheological fluid dampers to protect a data-logging equipment payload of a data-logging truck from vibration and/or impulse shock forces.

Abstract: A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

Abstract: A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

Abstract: A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.

Abstract: A method of receiving communications at a data processing device includes receiving a packet from a virtual channel associated with a physical communication link. The packet is associated with a link virtual channel, and is stored in a storage location with the link virtual channel. Multiple internal virtual channels can be associated with the link virtual channel. A pointer to the storage location is enqueued in one of a plurality of FIFOs associated with one of the internal virtual channels. Each FIFO of the plurality of FIFOs stores pointers associated with a different internal virtual channel, allowing receiver arbitration logic to reorder between internal virtual channels based on internal resource availability and current priorities among virtual channels. This reduces the likelihood of communication deadlock and supports multiple classes of service.

Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

Abstract: A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate.

Abstract: A processing node tracks probe activity level associated with its internal caching or memory system. If the probe activity level increases above a threshold probe activity level, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. After entering the higher performance state in response to the probe activity level being above the threshold probe activity level, the processing nodes returns to a lower performance state in response to a reduction in probe activity. There may be multiple threshold probe activity levels and associated performance states.

Abstract: A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.

Abstract: A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.

Abstract: A method of receiving communications at a data processing device includes receiving a packet from a virtual channel associated with a physical communication link. The packet is associated with a link virtual channel, and is stored in a storage location with the link virtual channel. Multiple internal virtual channels can be associated with the link virtual channel. A pointer to the storage location is enqueued in one of a plurality of FIFOs associated with one of the internal virtual channels. Each FIFO of the plurality of FIFOs stores pointers associated with a different internal virtual channel, allowing receiver arbitration logic to reorder between internal virtual channels based on internal resource availability and current priorities among virtual channels. This reduces the likelihood of communication deadlock and supports multiple classes of service.

Abstract: A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. Each unidirectional link forms a point-to-point interconnect to transfer packetized information between two processing nodes. A lock acquisition request from a lock requesting node is placed into service by an arbitrating node when no previous lock requests are pending for service. The arbitrating node transmits a broadcast message to all nodes in the system, which, in turn, respond with a corresponding probe response message to inform the arbitrating node of cessation of issuance of new requests by the node sending the probe response message. The arbitrating node informs the lock requesting node of the requesting node's lock ownership by transmitting a target done message thereto.

Abstract: A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more training patterns are transmitted over the first portion, while the second portion remains in the normal operational mode. An indication when to activate and deactivate the refresh mode may be sent over the second portion of the communication link. The refresh mode may be periodically entered from the power savings mode based on an interval register specifying the amount of time the communication link should remain in the power savings mode before a refresh occurs. In addition, the amount of time spent in the refresh mode may be programmable.