Patents by Inventor Jonathan Mark Audy

Jonathan Mark Audy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120313716
    Abstract: An oscillator synchronization system employs two oscillators, each of which includes an integrator which provides a ramping signal at its output, a comparator which receives the ramping signal and a reference signal at respective inputs and toggles an output when the ramping voltage crosses the reference signal, and a one-shot circuit that generates the integrator's reset signal when triggered. The system is preferably arranged such that the oscillators can be operated independently, in which case each oscillator's one-shot is triggered by its own comparator output, or synchronously, in which case each oscillator's one-shot is triggered by the other oscillator's comparator output—with the ramp signal of each oscillator operating to reset the integrator of the other oscillator. The oscillators are typically out-of-phase when synchronized, with the phase difference varying with the magnitude of the reference signals applied to the comparators.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Inventor: JONATHAN MARK AUDY
  • Patent number: 8319567
    Abstract: An oscillator synchronization system employs two oscillators, each of which includes an integrator which provides a ramping signal at its output, a comparator which receives the ramping signal and a reference signal at respective inputs and toggles an output when the ramping voltage crosses the reference signal, and a one-shot circuit that generates the integrator's reset signal when triggered. The system is preferably arranged such that the oscillators can be operated independently, in which case each oscillator's one-shot is triggered by its own comparator output, or synchronously, in which case each oscillator's one-shot is triggered by the other oscillator's comparator output—with the ramp signal of each oscillator operating to reset the integrator of the other oscillator. The oscillators are typically out-of-phase when synchronized, with the phase difference varying with the magnitude of the reference signals applied to the comparators.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: November 27, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Jonathan Mark Audy
  • Patent number: 8129862
    Abstract: A scalable highest available voltage selector circuit determines the highest of n input voltages and connects the highest voltage to an output. The circuit has at least n circuit branches, each of which comprises n?1 “comparator” FETs connected between an input voltage and an output node, and a diode-connected FET connected between the output node and a current source. The junction of the diode-connected transistor and current source provides a control signal used by the other branches. Each of a branch's comparator FETs have their gates connected to a respective one of the other branches' control signals, such that they are driven on regeneratively when the applied input voltage is the highest of the n input voltages. Each branch also includes n?1 “shorting” FETs connected across the diode-connected transistor, arranged to be driven off when the applied input voltage is the highest, but which are otherwise driven on.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: March 6, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Jonathan Mark Audy
  • Patent number: 8129972
    Abstract: A single integrator sensorless current mode control scheme for a switching power converter requires an amplifier circuit which produces an first current that varies with the difference Verror between a reference voltage and a voltage that varies proportionally with Vout, a circuit which produces a second current that varies with the voltage VL across the output inductor, a single integrating element connected to receive the first and second currents such that it integrates both Verror and VL, and a comparator which receives the integrated output at its first input and a substantially fixed voltage at its second input and produces an output that toggles when the voltage at its first input increases above and falls below the substantially fixed voltage. The comparator output is used to control the operation of the power converter's switching circuit and thereby regulate the output voltage.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: March 6, 2012
    Assignee: Analog Devices, Inc
    Inventor: Jonathan Mark Audy
  • Publication number: 20110095614
    Abstract: A scalable highest available voltage selector circuit determines the highest of n input voltages and connects the highest voltage to an output. The circuit has at least n circuit branches, each of which comprises n?1 “comparator” FETs connected between an input voltage and an output node, and a diode-connected FET connected between the output node and a current source. The junction of the diode-connected transistor and current source provides a control signal used by the other branches. Each of a branch's comparator FETs have their gates connected to a respective one of the other branches' control signals, such that they are driven on regeneratively when the applied input voltage is the highest of the n input voltages. Each branch also includes n?1 “shorting” FETs connected across the diode-connected transistor, arranged to be driven off when the applied input voltage is the highest, but which are otherwise driven on.
    Type: Application
    Filed: October 23, 2009
    Publication date: April 28, 2011
    Inventor: JONATHAN MARK AUDY
  • Publication number: 20090146634
    Abstract: A single integrator sensorless current mode control scheme for a switching power converter requires an amplifier circuit which produces an first current that varies with the difference Verror between a reference voltage and a voltage that varies proportionally with Vout, a circuit which produces a second current that varies with the voltage VL across the output inductor, a single integrating element connected to receive the first and second currents such that it integrates both Verror and VL, and a comparator which receives the integrated output at its first input and a substantially fixed voltage at its second input and produces an output that toggles when the voltage at its first input increases above and falls below the substantially fixed voltage. The comparator output is used to control the operation of the power converter's switching circuit and thereby regulate the output voltage.
    Type: Application
    Filed: October 31, 2008
    Publication date: June 11, 2009
    Inventor: Jonathan Mark Audy