Abstract: A mechanism for detection and measurement of hardware-based processor latency is disclosed. A method of the invention includes issuing an instruction to stop all running instructions on one or more processors of a multi-core computing device, starting a latency measurement code loop on each of the one or more processors, wherein for each of the one or more processors the latency measurement code loop operates to sample a time stamp counter (TSC) for a first time reading and sample the TSC for a second time reading after a predetermined period of time, and determine whether a difference between the first and the second time readings represents a discontinuous time interval where an operating system (OS) of the computing device does not control the one or more processors.

Abstract: A data connection between a server and an application running on a mobile telephone handset is used to provide caption text of a telephonic conversation between call participants to the mobile phone handset during an active telephone call. Prior to providing the captions, a communication session between the server and the application running on the handset, the means of transporting the caption text is determined. Transport may be by way of data socket connection or by way of SMS messages.