Abstract: A method of controlling memory read behavior in PCI devices includes connecting a master PCI device to a PCI bus. The master PCI device is constructed and arranged to issue a Memory Read Line or a Memory Read Multiple initial command. A target PCI bridge device is connected to the PCI bus. The target PCI bridge device is constructed and arranged to prefetch data from host memory on behalf of the master PCI device and to store the prefetched data. A data transfer transaction is established between the master PCI device and the target PCI bridge device and prefetched data is stored at the target PCI bridge device. A bit is selectively preset in at least one of the PCI devices such that if a disconnect of the transaction occurs, the target PCI bridge device recognizes a subsequent request as a continuation of the initial request and sends prefetched data to the master PCI device.

Abstract: Buffer-level arbitration is used to allocate released buffers, based on received flow control credits, between local packets and received packets on respective virtual channels in accordance with a determined insertion rate relative to a second number of received packets to be forwarded. Virtual channel arbitration also is performed to identify, from among the multiple virtual channels, the packets that should be sent next along the local and forwarded paths. Device arbitration is then performed to identify, from the insertion and forwarding paths, the packets that should be output onto an output transmission link, based on the determined insertion rate. Performing the arbitration at each step in accordance with the insertion rate maximizes packet bandwidth fairness among the multiple devices supplying packets across multiple virtual channels.

Abstract: Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference clock signal, marked by the assertion of a periodic sync signal. The periodic sync signal, synchronous with the source clock, is used to output to an unload pointer counter in the target clock domain the deassertion of a reset signal prior to the nominal alignment of the source clock and the target clock for sampling on the nominally aligned target clock edge. The deassertion of the reset signal is output to a load pointer in the source clock domain coincident with the nominally-aligned edges of the source clock and the target clock. Both loading and unloading start based on the reset deassertion being sampled on the nominally aligned edges in the appropriate clock domain.

Abstract: Precise estimation of latency is attained based on identifying that a receive clock is configured to operate only at prescribed available frequencies. A receive buffer circuit includes buffer control logic configured for reading a selected number of the buffer entries based on a detected number of receive clock edges within one local clock cycle. Valid data is identified based on the number of clock edges exceeding a selected threshold. A selected pointer offset is obtained from a lookahead table, specifying multiple pointer offsets for accommodating latency encountered at respective prescribed available frequencies, based on matching the determined frequency to one of the prescribed available frequencies. The selected pointer offset is added to a read pointer to offset the latency encountered from edge detection.