Abstract: A manufacturing process includes: depositing a first catalyst on a first gas diffusion layer (GDL) to form a first catalyst-coated GDL; depositing a first ionomer on the first catalyst-coated GDL to form a first gas diffusion electrode (GDE); depositing a second catalyst on a second GDL to form a second catalyst-coated GDL; depositing a second ionomer on the second catalyst-coated GDL to form a second GDE; and laminating the first GDE with the second GDE and with an electrolyte membrane disposed between the first GDE and the second GDE to form a membrane electrode assembly (MEA). A MEA includes a first GDL; a second GDL; an electrolyte membrane disposed between the first GDL and the second GDL; a first catalyst layer disposed between the first GDL and the electrolyte membrane; and a second catalyst layer disposed between the second GDL and the electrolyte membrane, wherein a thickness of the electrolyte membrane is about 15 ?m or less.

Abstract: A manufacturing process includes: depositing a first catalyst on a first gas diffusion layer (GDL) to form a first catalyst-coated GDL; depositing a first ionomer on the first catalyst-coated GDL to form a first gas diffusion electrode (GDE); depositing a second catalyst on a second GDL to form a second catalyst-coated GDL; depositing a second ionomer on the second catalyst-coated GDL to form a second GDE; and laminating the first GDE with the second GDE and with an electrolyte membrane disposed between the first GDE and the second GDE to form a membrane electrode assembly (MEA). A MEA includes a first GDL; a second GDL; an electrolyte membrane disposed between the first GDL and the second GDL; a first catalyst layer disposed between the first GDL and the electrolyte membrane; and a second catalyst layer disposed between the second GDL and the electrolyte membrane, wherein a thickness of the electrolyte membrane is about 15 ?m or less.

Abstract: A peg for the use in a construction industry is disclosed. The peg may include: a main longitudinal body configured to be inserted into a solid surface, and an indicator. The indicator may be configured to adaptively present visual quantitative information related to at least one of: a tip of the peg and construction task instructions. The indicator may include a scale notches for marking height such that the scale notches may be marked on at least a portion of the main longitudinal body. The peg may further include a marker for adaptively marking the solid surface related information.

Abstract: A manufacturing process includes: depositing a first catalyst on a first gas diffusion layer (GDL) to form a first catalyst-coated GDL; depositing a first ionomer on the first catalyst-coated GDL to form a first gas diffusion electrode (GDE); depositing a second catalyst on a second GDL to form a second catalyst-coated GDL; depositing a second ionomer on the second catalyst-coated GDL to form a second GDE; and laminating the first GDE with the second GDE and with an electrolyte membrane disposed between the first GDE and the second GDE to form a membrane electrode assembly (MEA). A MEA includes a first GDL; a second GDL; an electrolyte membrane disposed between the first GDL and the second GDL; a first catalyst layer disposed between the first GDL and the electrolyte membrane; and a second catalyst layer disposed between the second GDL and the electrolyte membrane, wherein a thickness of the electrolyte membrane is about 15 ?m or less.

Abstract: Device comprising processing means (MT), transmission channels (VE1, . . . VEn), an antenna array for transmitting signals comprising a number of antennas (A11 . . . A1n) respectively associated with the transmission channels, a number of digital-analog converters (DAC) and a number of phase-shifting means (MD1, . . . MDn) respectively associated with the antennas, said phase-shifting means (MD1, . . . MDn) being placed between the processing means (MT) and the digital-analog converters (DAC) and including digital all-pass filters of FIR type (PT), the processing means comprising control means (MC) configured to adjust the coefficients and/or the order of the all-pass filters of FIR type.

Abstract: Examples are provided for converting an analog signal to a digital output signal using serial-ripple analog-to-digital conversion (ADC). An ADC circuit may include conversion stages coupled in series. Each conversion stage may generate a bit for the digital output signal. A data latch may receive bits for the digital output signal from the conversion stages and to provide the digital output signal based on the bits. A conversion stage may include a comparator circuit and a multiplexer circuit. The comparator circuit may compare a sampled input signal with a reference signal and to generate the associated bit of the digital output signal based on a result of the comparison. The multiplexer circuit may provide an associated reference signal to a comparator circuit of a next conversion stage, where the next conversion stage is subsequent to the conversion stage.

Abstract: Examples are provided for converting an analog signal to a digital output signal using serial-ripple analog-to-digital conversion (ADC). An ADC circuit may include conversion stages coupled in series. Each conversion stage may generate a bit for the digital output signal. A data latch may receive bits for the digital output signal from the conversion stages and to provide the digital output signal based on the bits. A conversion stage may include a comparator circuit and a multiplexer circuit. The comparator circuit may compare a sampled input signal with a reference signal and to generate the associated bit of the digital output signal based on a result of the comparison. The multiplexer circuit may provide an associated reference signal to a comparator circuit of a next conversion stage, where the next conversion stage is subsequent to the conversion stage.

Abstract: Examples of resistive digital-to-analog converter (RDAC) circuits are provided herein. RDAC circuits may provide an analog output signal derived from an n-bit digital input signal. In one example, an RDAC circuit may include a plurality of resistive circuit branches. Each resistive circuit branch may be arranged in a pull up/pull down network configuration. For example, an RDAC circuit may include a plurality of resistive circuit branches positioned in parallel. In an example, each of the plurality of resistive circuit branches may include a first inverter circuit, a second inverter circuit, and a resistive component. The RDAC circuit may include an output node for providing the analog output signal. Additionally, methods are provided for converting an analog output signal derived from an n-bit digital input signal.

Abstract: Examples of resistive digital-to-analog converter (RDAC) circuits are provided herein. RDAC circuits may provide an analog output signal derived from an n-bit digital input signal. In one example, an RDAC circuit may include a plurality of resistive circuit branches. Each resistive circuit branch may be arranged in a pull up/pull down network configuration. For example, an RDAC circuit may include a plurality of resistive circuit branches positioned in parallel. In an example, each of the plurality of resistive circuit branches may include a first inverter circuit, a second inverter circuit, and a resistive component. The RDAC circuit may include an output node for providing the analog output signal. Additionally, methods are provided for converting an analog output signal derived from an n-bit digital input signal.

Abstract: Device comprising processing means (MT), transmission channels (VE1, . . . VEn), an antenna array for transmitting signals comprising a number of antennas (A11 . . . A1n) respectively associated with the transmission channels, a number of digital-analogue converters (DAC) and a number of phase-shifting means (MD1, . . . MDn) respectively associated with the antennas, said phase-shifting means (MD1, . . . MDn) being placed between the processing means (MT) and the digital-analogue converters (DAC) and including digital all-pass filters of FIR type (PT), the processing means comprising control means (MC) configured to adjust the coefficients and/or the order of the all-pass filters of FIR type.