Patents by Inventor Jonathan P. Davis

Jonathan P. Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230420258
    Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.
    Type: Application
    Filed: July 5, 2023
    Publication date: December 28, 2023
    Inventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
  • Patent number: 11742208
    Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: August 29, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
  • Patent number: 11443879
    Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Fuchao Wang, Yousong Zhang, Neal Thomas Murphy, Brian Zinn, Jonathan P. Davis
  • Publication number: 20210305050
    Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.
    Type: Application
    Filed: March 25, 2020
    Publication date: September 30, 2021
    Applicant: Texas Instruments Incorporated
    Inventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
  • Publication number: 20190341181
    Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: Fuchao Wang, Yousong Zhang, Neal Thomas Murphy, Brian Zinn, Jonathan P. Davis
  • Patent number: 10403424
    Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: September 3, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Fuchao Wang, Yousong Zhang, Neal Thomas Murphy, Brian Zinn, Jonathan P. Davis
  • Publication number: 20180358163
    Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Fuchao Wang, Yousong Zhang, Neal Thomas Murphy, Brian Zinn, Jonathan P. Davis
  • Patent number: 6472291
    Abstract: A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention includes providing a semiconductor wafer having trenches formed in a trench region of a substrate, and forming a dielectric layer on the semiconductor wafer to fill the trenches whereby up features form on flat surfaces of the wafer. An edge portion of the semiconductor wafer is polished to remove a portion of the dielectric layer about the edge portions of the semiconductor wafer. The dielectric layer is polished across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the trench regions and the up features in a single polish step such that a mask step and etch step for reducing the up features are eliminated from the polishing process.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: October 29, 2002
    Assignees: Infineon Technologies North America Corp., Infineon Technologies Richmond, LP, Motorola, Inc.
    Inventors: Joseph E. Page, Jonathan P. Davis, Scott W. Bailey
  • Patent number: 4583596
    Abstract: A seat coacting with the flapper of a subsurface well safety valve which includes a solid metal annular seat and an annular flexible metal seal in a recess about the solid seat. The flexible seal has a base secured in the recess and a resilient sealing lip which is generally V-shaped in cross section with one end of one of the legs of the V being connected to the base and sealing against the side of the recess and the other leg extending downwardly beyond the solid seat for making contact with the flapper before the flapper seats on the solid seat. The solid seat and the sealing lip are directed downwardly at an angle with the angle of the sealing lip being greater than the angle of the solid seat.
    Type: Grant
    Filed: September 13, 1985
    Date of Patent: April 22, 1986
    Assignee: Camco, Incorporated
    Inventor: Jonathan P. Davis