Abstract: One example aspect of the present disclosure is directed to a method for scheduling a message. The method includes receiving, by one or more processors, an offset and an interval associated with a virtual link. The method includes receiving, by the one or more processors, an absolute count representing a start time. The method includes designating, by the one or more processors, a plurality of transfer times for the virtual link as a function of the offset and the interval. The method includes receiving, by the one or more processors, a message associated with the virtual link at a first time. The method includes transmitting, by the one or more processors, the message at a next transfer time in the plurality of transfer times.

Abstract: One example aspect of the present disclosure is directed to a method for scheduling a message. The method includes receiving, by one or more processors, an offset and an interval associated with a virtual link. The method includes receiving, by the one or more processors, an absolute count representing a start time. The method includes designating, by the one or more processors, a plurality of transfer times for the virtual link as a function of the offset and the interval. The method includes receiving, by the one or more processors, a message associated with the virtual link at a first time. The method includes transmitting, by the one or more processors, the message at a next transfer time in the plurality of transfer times.

Abstract: Systems and methods for providing an efficient and configurable port interface in an avionics data transfer system are provided. For instance, in one embodiment a set of virtual ports associated with an avionics data transfer system can be defined. At least as a subset of the virtual ports can be mapped to one or more addresses in a memory space associated with the data transfer system, such that each virtual port has a fixed definition in the memory space. One or more of the virtual ports can then be associated with one or more physical ports associated with an interface between a host computing device and an end system in the data transfer system by specifying for the one or more virtual ports a plurality of port parameters that define the respective one or more physical ports.

Abstract: Systems and methods for providing an efficient and configurable port interface in an avionics data transfer system are provided. For instance, in one embodiment a set of virtual ports associated with an avionics data transfer system can be defined. At least as a subset of the virtual ports can be mapped to one or more addresses in a memory space associated with the data transfer system, such that each virtual port has a fixed definition in the memory space. One or more of the virtual ports can then be associated with one or more physical ports associated with an interface between a host computing device and an end system in the data transfer system by specifying for the one or more virtual ports a plurality of port parameters that define the respective one or more physical ports.

Abstract: A method of providing synchronization and integrity checking in a high integrity processing system having at least two redundant processing lanes, with each lane having an application processor, with the application processors running the same application software in a non-lockstep configuration, and outputting transactions requiring access to an addressable space.

Abstract: A method of providing synchronization and integrity checking in a high integrity processing system having at least two redundant processing lanes, with each lane having an application processor, with the application processors running the same application software in a non-lockstep configuration, and outputting transactions requiring access to an addressable space.

Abstract: A method of providing synchronization and integrity checking in a high integrity processing system having at least two redundant processing lanes, with each lane having an application processor, with the application processors running the same application software in a non-lockstep configuration, and outputting transactions requiring access to an addressable space.

Abstract: A method of providing synchronization and integrity checking in a high integrity processing system having at least two redundant processing lanes, with each lane having an application processor, with the application processors running the same application software in a non-lockstep configuration, and outputting transactions requiring access to an addressable space.