Abstract: An apparatus and method for efficiently processing invariant operations on a parallel execution engine.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: An apparatus and method for offloading iterative, parallel work to a data parallel cluster. For example, one embodiment of a processor comprises: a host processor to execute a primary thread; a data parallel cluster coupled to the host processor over a high speed interconnect, the data parallel cluster comprising a plurality of execution lanes to perform parallel execution of one or more secondary threads related to the primary thread; and a data parallel cluster controller integral to the host processor to offload processing of the one or more secondary threads to the data parallel cluster in response to one of the cores executing a parallel processing call instruction from the primary thread.

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

Abstract: An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule matrix operations responsive to a matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, wherein a lane comprises an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are to be stored in registers within the lane; and broadcast circuitry to broadcast one or more invariant matrix blocks to at least one of different registers within the lane and different registers across different lanes.

Abstract: An apparatus and method for data parallel single program multiple data (SPMD) execution. For example, one embodiment of a processor comprises: instruction fetch circuitry to fetch instructions of one or more primary threads; a decoder to decode the instructions to generate uops; a data parallel cluster (DPC) to execute microthreads comprising a subset of the uops, the DPC further comprising: a plurality of execution lanes to perform parallel execution of the microthreads; an instruction decode queue (IDQ) to store the uops prior to execution; and a scheduler to evaluate the microthreads based on associated variables including instruction pointer (IP) values, the scheduler to gang microthreads into fragments for parallel execution on the execution lanes based on the evaluation.

Abstract: Embodiments are generally directed to thread group scheduling for graphics processing. An embodiment of an apparatus includes a plurality of processors including a plurality of graphics processors to process data; a memory; and one or more caches for storage of data for the plurality of graphics processors, wherein the one or more processors are to schedule a plurality of groups of threads for processing by the plurality of graphics processors, the scheduling of the plurality of groups of threads including the plurality of processors to apply a bias for scheduling the plurality of groups of threads according to a cache locality for the one or more caches.

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

Abstract: An apparatus and method for performing efficient, adaptable tensor operations.

Abstract: An apparatus and method for offloading iterative, parallel work to a data parallel cluster. For example, one embodiment of a processor comprises: a host processor to execute a primary thread; a data parallel cluster coupled to the host processor over a high speed interconnect, the data parallel cluster comprising a plurality of execution lanes to perform parallel execution of one or more secondary threads related to the primary thread; and a data parallel cluster controller integral to the host processor to offload processing of the one or more secondary threads to the data parallel cluster in response to one of the cores executing a parallel processing call instruction from the primary thread.

Abstract: An apparatus and method for data parallel single program multiple data (SPMD) execution. For example, one embodiment of a processor comprises: instruction fetch circuitry to fetch instructions of one or more primary threads; a decoder to decode the instructions to generate uops; a data parallel cluster (DPC) to execute microthreads comprising a subset of the uops, the DPC further comprising: a plurality of execution lanes to perform parallel execution of the microthreads; an instruction decode queue (IDQ) to store the uops prior to execution; and a scheduler to evaluate the microthreads based on associated variables including instruction pointer (IP) values, the scheduler to gang microthreads into fragments for parallel execution on the execution lanes based on the evaluation.

Abstract: An apparatus and method for performing efficient, adaptable tensor operations.

Abstract: Organopolysulfides such as organodisulfides, organotrisulfides and/or organotetrasulfides are useful stabilizers for polymer compositions, wherein the tendency of a polymer to degrade when exposed to environmental conditions such as heat, light and oxygen may be ameliorated by the incorporation of one or more of such organopolysulfides, optionally together with one or more additional stabilization additives such as a hindered phenol antioxidant, phosp(on)ite stabilizer or hindered amine light stabilizer.

Abstract: An apparatus and method for efficiently processing invariant operations on a parallel execution engine.

Abstract: Efficient heuristic methods are described for approximating the optimal leader strategy for security domains where threats come from unknown adversaries. These problems can be modeled as Bayes-Stackelberg games. An embodiment of the heuristic method can include defining a patrolling or security domain problem as a mixed-integer quadratic program. The mixed-integer quadratic program can be converted to a mixed-integer linear program. For a single follower (e.g., robber or terrorist) scenario, the mixed-integer linear program can be solved, subject to appropriate constraints. For embodiments applicable to multiple follower situations, the relevant mixed-integer quadratic program and related mixed-integer linear program can be decomposed, e.g., by changing the response function for the follower from a pure strategy to a weighted combination over various pure follower strategies where the weights are probabilities of occurrence of each of the follower types.

Abstract: Efficient heuristic methods are described for approximating the optimal leader strategy for security domains where threats come from unknown adversaries. These problems can be modeled as Bayes-Stackelberg games. An embodiment of the heuristic method can include defining a patrolling or security domain problem as a mixed-integer quadratic program. The mixed-integer quadratic program can be converted to a mixed-integer linear program. For a single follower (e.g., robber or terrorist) scenario, the mixed-integer linear program can be solved, subject to appropriate constraints. For embodiments applicable to multiple follower situations, the relevant mixed-integer quadratic program and related mixed-integer linear program can be decomposed, e.g., by changing the response function for the follower from a pure strategy to a weighted combination over various pure follower strategies where the weights are probabilities of occurrence of each of the follower types.

Abstract: Techniques are described for Stackelberg games, in which one agent (the leader) must commit to a strategy that can be observed by other agents (the followers or adversaries) before they choose their own strategies, in which the leader is uncertain about the types of adversaries it may face. Such games are important in security domains, where, for example, a security agent (leader) must commit to a strategy of patrolling certain areas, and robbers (followers) have a chance to observe this strategy over time before choosing their own strategies of where to attack. An efficient exact algorithm is described for finding the optimal strategy for the leader to commit to in these games. This algorithm, Decomposed Optimal Bayesian Stackelberg Solver or “DOBSS,” is based on a novel and compact mixed-integer linear programming formulation. The algorithm can be implemented in a method, software, and/or system including computer or processor functionality.

Abstract: Efficient heuristic methods are described for approximating the optimal leader strategy for security domains where threats come from unknown adversaries. These problems can be modeled as Bayes-Stackelberg games. An embodiment of the heuristic method can include defining a patrolling or security domain problem as a mixed-integer quadratic program. The mixed-integer quadratic program can be converted to a mixed-integer linear program. For a single follower (e.g., robber or terrorist) scenario, the mixed-integer linear program can be solved, subject to appropriate constraints. For embodiments applicable to multiple follower situations, the relevant mixed-integer quadratic program and related mixed-integer linear program can be decomposed, e.g., by changing the response function for the follower from a pure strategy to a weighted combination over various pure follower strategies where the weights are probabilities of occurrence of each of the follower types.

Abstract: Efficient heuristic methods are described for approximating the optimal leader strategy for security domains where threats come from unknown adversaries. These problems can be modeled as Bayes-Stackelberg games. An embodiment of the heuristic method can include defining a patrolling or security domain problem as a mixed-integer quadratic program. The mixed-integer quadratic program can be converted to a mixed-integer linear program. For a single follower (e.g., robber or terrorist) scenario, the mixed-integer linear program can be solved, subject to appropriate constraints. For embodiments applicable to multiple follower situations, the relevant mixed-integer quadratic program and related mixed-integer linear program can be decomposed, e.g., by changing the response function for the follower from a pure strategy to a weighted combination over various pure follower strategies where the weights are probabilities of occurrence of each of the follower types.

Abstract: Techniques are described for Stackelberg games, in which one agent (the leader) must commit to a strategy that can be observed by other agents (the followers or adversaries) before they choose their own strategies, in which the leader is uncertain about the types of adversaries it may face. Such games are important in security domains, where, for example, a security agent (leader) must commit to a strategy of patrolling certain areas, and robbers (followers) have a chance to observe this strategy over time before choosing their own strategies of where to attack. An efficient exact algorithm is described for finding the optimal strategy for the leader to commit to in these games. This algorithm, Decomposed Optimal Bayesian Stackelberg Solver or “DOBSS,” is based on a novel and compact mixed-integer linear programming formulation. The algorithm can be implemented in a method, software, and/or system including computer or processor functionality.