Abstract: A method and structure is presented for a display with reduced size pixels while retaining the transmissive approach. This enables continued use the least expensive transmission optics available. In an embodiment, it employs back-end-of-the-line vertical cells built on top of the row and column x, y lines of the pixels. In a PDLC type display embodiment each vertical cell is filled with PDLC which operates in a normally black mode known as the PDLC reverse mode. When the pixel control voltage is set ON, the liquid crystal is perpendicular to the light path resulting in a light pass through providing a bright state. When the control voltage is set OFF, the liquid crystals are randomly oriented, only the scattered light goes through the cell, so the pixel is in its OFF state. PDLC used here has two advantages. Firstly, the PDLC requires no rubbing. It is difficult to rub individual cell walls. Secondly, the use of both polarizations by the PDLC increases its luminous efficiency.

Abstract: This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings.