Patents by Inventor Jonathan Perry

Jonathan Perry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260119400
    Abstract: In an aspect, an apparatus comprises a writer agent, wherein the writer agent may obtain exclusive access to at least one coherence granule of shared memory with respect to one or more other agents. The writer agent may mark, at the writer agent, completion of a store of the at least one coherence granule prior to receipt of data for the at least one coherence granule from the shared memory. The writer agent may receive the data from the shared memory for the at least one coherence granule. The writer agent may store the data at a local cache of the writer agent. The writer agent may modify the data at the writer agent.
    Type: Application
    Filed: October 31, 2024
    Publication date: April 30, 2026
    Inventor: Jonathan PERRY
  • Publication number: 20260120071
    Abstract: A draw lottery ticket selling system and methods of operating the system that enable the purchase of draw lottery tickets by players, and the remote printing of the draw lottery tickets using different devices.
    Type: Application
    Filed: October 29, 2024
    Publication date: April 30, 2026
    Inventors: Paul Schneider, Sridhar Jawaharlal, Corey Edwards, Jonathan Perry, David Antolino Rivas, Ratheesh Nair
  • Publication number: 20260056745
    Abstract: Disclosed is a prefetcher, e.g., of a system with one or more cores. The prefetcher determines data dependency access (DDA) patterns, such as array indirect access, and prefetches data based on the DDA patterns.
    Type: Application
    Filed: August 22, 2024
    Publication date: February 26, 2026
    Inventors: Abanti BASAK, Aarti CHANDRASHEKHAR, Mahesh MADHAV, Jonathan PERRY, Eric SCHWARTZ, David TURLEY
  • Patent number: 10860319
    Abstract: An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Mark Dechene, Manjunath Shevgoor, Faruk Guvenilir, Zhongying Zhang, Jonathan Perry
  • Publication number: 20190311117
    Abstract: A computer implemented method of detecting execution of unregistered code in a protected networked system, comprising maintaining a pages registry record in a storage of an endpoint in a protected networked system, the pages registry record comprising a registration signature for each of a plurality of registered executable pages, monitoring a plurality of executable pages at a page management level using an adjusted page fault handler of an operating system kernel executed by one or more processors of the endpoint, detecting one or more unregistered executable pages by identifying incompliance of a runtime signature calculated in runtime for the unregistered executable page(s) with respective registration signature stored in the pages registry record and initiating one or more actions in case of the detection of the unregistered executable page(s).
    Type: Application
    Filed: June 14, 2017
    Publication date: October 10, 2019
    Applicant: Cymmetria, Inc.
    Inventors: Dean SYSMAN, Imri GOLDBERG, Itamar SHER, Jonathan PERRY, Shmuel UR
  • Publication number: 20190303150
    Abstract: An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Mark Dechene, Manjunath Shevgoor, Faruk Guvenilir, Zhongying Zhang, Jonathan Perry
  • Patent number: 10348600
    Abstract: Among other things, flow rates of traffic among endpoints in a network are controlled. Notifications are received about flowlets originating or received at the endpoints. Each of the flowlets includes one or more packets that are in a queue associated with a corresponding flowlet. In response to the received notifications, updated flow rates are computed for the flowlets. The updated flow rates are sent to devices for use in controlling flow rates for the flowlets in accordance with the computed updated flow rates.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 9, 2019
    Assignee: Flowtune, Inc.
    Inventor: Jonathan Perry
  • Publication number: 20170230298
    Abstract: Among other things, flow rates of traffic among endpoints in a network are controlled. Notifications are received about flowlets originating or received at the endpoints. Each of the flowlets includes one or more packets that are in a queue associated with a corresponding flowlet. In response to the received notifications, updated flow rates are computed for the flowlets. The updated flow rates are sent to devices for use in controlling flow rates for the flowlets in accordance with the computed updated flow rates. Also, rates of flow at endpoints of a network are controlled. A device in the network sends notification of a start or end of a flowlet at an endpoint of the network. The notification is sent to an allocator to which other devices send notifications with respect to other flowlets. At the device, a communication rate is received from the allocator. The rate is one of a set of communication rates for flowlets starting and ending at endpoints of the network.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 10, 2017
    Applicant: Flowtune, Inc.
    Inventor: Jonathan Perry
  • Patent number: 9270412
    Abstract: Described herein are new error-correction (channel) codes: permute codes, iterative ensembles of permute and spinal codes, and graphical hash codes. In one aspect, a wireless system includes an encoder configured to encode data using one of the aforementioned channel codes. The wireless system also includes a decoder configured to decode the encoded data.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: February 23, 2016
    Assignee: Massachusetts Institute of Technology
    Inventors: Jonathan Perry, Hari Balakrishnan, Devavrat D. Shah
  • Patent number: 9143175
    Abstract: In one aspect, a wireless system includes an encoder configured to encode data using a spinal code which uses a function over the message bits to directly produce a sequence of constellation symbols for transmission. The wireless system also includes a decoder configured to decode the spinal code. The function may be at least one of a non-linear function and a hash function.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 22, 2015
    Assignee: Massachusetts Institute of Technology
    Inventors: Jonathan Perry, Devavrat Shah, Hari Balakrishnan
  • Publication number: 20150003557
    Abstract: Described herein are new error-correction (channel) codes: permute codes, iterative ensembles of permute and spinal codes, and graphical hash codes. In one aspect, a wireless system includes an encoder configured to encode data using one of the aforementioned channel codes. The wireless system also includes a decoder configured to decode the encoded data.
    Type: Application
    Filed: June 25, 2014
    Publication date: January 1, 2015
    Applicant: Massachusetts Institute of Technology
    Inventors: Jonathan Perry, Hari Balakrishnan, Devavrat D. Shah
  • Publication number: 20140211881
    Abstract: In one aspect, a wireless system includes an encoder configured to encode data using a spinal code which uses a function over the message bits to directly produce a sequence of constellation symbols for transmission. The wireless system also includes a decoder configured to decode the spinal code. The function may be at least one of a non-linear function and a hash function.
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Jonathan Perry, Devavrat Shah, Hari Balakrishnan
  • Patent number: 8724715
    Abstract: In one aspect, a wireless system includes an encoder configured to encode data using a spinal code which uses a function over the message bits to directly produce a sequence of constellation symbols for transmission. The wireless system also includes a decoder configured to decode the spinal code. The function may be at least one of a non-linear function and a hash function.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 13, 2014
    Assignee: Massachusetts Institute of Technology
    Inventors: Jonathan Perry, Devavrat Shah, Hari Balakrishnan
  • Publication number: 20120213307
    Abstract: In one aspect, a wireless system includes an encoder configured to encode data using a spinal code which uses a function over the message bits to directly produce a sequence of constellation symbols for transmission. The wireless system also includes a decoder configured to decode the spinal code. The function may be at least one of a non-linear function and a hash function.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 23, 2012
    Applicant: Massachusetts Institute of Technology
    Inventors: Jonathan Perry, Devavrat Shah, Hari Balakrishnan
  • Patent number: D902304
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: November 17, 2020
    Inventors: Jonathan Perry, Chieh-Yu Lin