Abstract: A system, according to one embodiment, includes a first end having several first contacts configured for coupling with a circuit board, a second end oriented about orthogonal to the first end, and a plurality of leads connecting the first and second contacts. The second end has a plurality of second contacts configured for coupling directly with a card edge of an electronic device. The orientation of the second end relative to the first end is fixed. A system, according to another embodiment, includes a circuit board, a plurality of such connectors.

Abstract: In one general embodiment, a system includes a first end having a plurality of first contacts configured for coupling with a circuit device, and a second end having a plurality of second contacts configured for coupling directly with a card edge of an electronic device. The system also includes a plurality of leads extending between the first and second contacts. A heat spreader plate extends along the leads between the first and second ends, the heat spreader plate having at least one of: a conducting pad extending beyond the first end and a conducting pad extending beyond the second end.

Abstract: A system, according to one embodiment, includes a first end having several first contacts configured for coupling with a circuit board, a second end oriented about orthogonal to the first end, and a plurality of leads connecting the first and second contacts. The second end has a plurality of second contacts configured for coupling directly with a card edge of an electronic device. The orientation of the second end relative to the first end is fixed. A system, according to another embodiment, includes a circuit board, a plurality of such connectors.

Abstract: A computing assembly comprises an enclosure body having opposite first and second planar surfaces, one or more storage bays operably coupled with the enclosure body (where the one or more storage bays pivot relative to the enclosure body to protrude outward from the first planar surface of the enclosure body), one or more computing node devices at least partially disposed within the enclosure body (where the one or more computing node devices include one or more circuits) and one or more memory devices disposed within the one or more storage bays.

Abstract: A method for improving safety of voltage regulator is disclosed. In order to improve safety of a voltage regulator, a MOS-FET is disposed on a source power lane that receives power supplied from a DC power supply. A set of voltage regulators is connected to a set of fork power lanes, correspondingly, branching off from the source power lane. PTC thermistors are disposed on a surface or in the vicinity of semiconductor chips of the voltage regulators. When temperature at any one of the PTC thermistors increases, a protection controller turns off the MOS-FET. When temperature detected by a temperature sensor incorporated within the semiconductor chip has increased, each of the voltage regulators turns off the MOS-FET via a base management controller.

Abstract: A computing assembly comprises an enclosure body having opposite first and second planar surfaces, one or more storage bays operably coupled with the enclosure body (where the one or more storage bays pivot relative to the enclosure body to protrude outward from the first planar surface of the enclosure body), one or more computing node devices at least partially disposed within the enclosure body (where the one or more computing node devices include one or more circuits) and one or more memory devices disposed within the one or more storage bays.

Abstract: Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.

Abstract: Memory systems and methods of forming memory modules. In one embodiment, a computer memory system includes a substantially tubular frame with an elongate card edge extending along the frame. A flexible circuit comprising a flexible substrate, a plurality of memory chips affixed to the flexible substrate, and a plurality of electrical terminals interconnected with the memory chips, is secured along a perimeter of the tubular frame with the electrical terminals arranged along the card edge.

Abstract: Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.

Abstract: Method and apparatus for installing a processor into electronic communication with a socket. The land grid array socket connector includes a socket housing secured to a circuit board and an array of upwardly extending pins for electronic communication with contact pads on the processor. The socket connector provides a carriage configured to receiving the processor through a lateral opening and support a perimeter edge of the processor. A mechanical linkage couples the carriage and the socket housing for substantially vertically translating the processor relative to the socket. A plurality of alignment features upwardly extends from the socket housing along the perimeter of the array of pins. Each of the alignment features has an inwardly-facing tapered surface for registering the edge of the processor and biasing the processor into a position where the array of contact pads are aligned with the array of pins as the processor is lowered.

Abstract: Method and apparatus for installing a processor into electronic communication with a socket. The land grid array socket connector includes a socket housing secured to a circuit board and an array of upwardly extending pins for electronic communication with contact pads on the processor. The socket connector provides a carriage configured to receiving the processor through a lateral opening and support a perimeter edge of the processor. A mechanical linkage couples the carriage and the socket housing for substantially vertically translating the processor relative to the socket. A plurality of alignment features upwardly extends from the socket housing along the perimeter of the array of pins. Each of the alignment features has an inwardly-facing tapered surface for registering the edge of the processor and biasing the processor into a position where the array of contact pads are aligned with the array of pins as the processor is lowered.

Abstract: An apparatus, system, and method are disclosed for caching fully buffered memory (FBM) data. A circuit card is connected to an FBM socket that is configured to receive a FBM. An interface module communicates with a memory controller and at least one FBM via the FBM socket through a plurality of electrical interfaces. A cache controller apportions memory space in the cache memory between each FBM of the at least one FBM according to an apportionment policy. A cache memory transparently stores data from the at least one FBM and the memory controller and transparently provides the data to the memory controller. The cache controller manages coherency between the at least one FBM and the cache memory.