Patents by Inventor Jonathan Redshaw
Jonathan Redshaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230419598Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.Type: ApplicationFiled: September 4, 2023Publication date: December 28, 2023Inventor: Jonathan Redshaw
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Publication number: 20230394615Abstract: A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.Type: ApplicationFiled: August 21, 2023Publication date: December 7, 2023Inventors: John Howson, Jonathan Redshaw, Yoong Chert Foo
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Publication number: 20230297425Abstract: A resource allocator receives a memory resource request for first memory resources in respect of a first-received task of a workgroup having a plurality of tasks. In response to receiving the memory resource request, the resource allocator allocates to the entire workgroup a block of memory portions of a shared memory that is sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.Type: ApplicationFiled: May 23, 2023Publication date: September 21, 2023Inventors: Luca Iuliano, Simon Nield, Yoong-Chert Foo, Ollie Mower, Jonathan Redshaw
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Patent number: 11748941Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.Type: GrantFiled: November 22, 2022Date of Patent: September 5, 2023Assignee: Imagination Technologies LimitedInventor: Jonathan Redshaw
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Patent number: 11734788Abstract: A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.Type: GrantFiled: October 29, 2021Date of Patent: August 22, 2023Assignee: Imagination Technologies LimitedInventors: John Howson, Jonathan Redshaw, Yoong Chert Foo
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Patent number: 11656908Abstract: A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.Type: GrantFiled: April 1, 2021Date of Patent: May 23, 2023Assignee: Imagination Technologies LimitedInventors: Luca Iuliano, Simon Nield, Yoong-Chert Foo, Ollie Mower, Jonathan Redshaw
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Publication number: 20230038653Abstract: An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.Type: ApplicationFiled: October 6, 2022Publication date: February 9, 2023Inventors: Xile Yang, John W. Howson, Jonathan Redshaw
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Patent number: 11538215Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.Type: GrantFiled: October 1, 2021Date of Patent: December 27, 2022Assignee: Imagination Technologies LimitedInventor: Jonathan Redshaw
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Patent number: 11481952Abstract: An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.Type: GrantFiled: September 30, 2020Date of Patent: October 25, 2022Assignee: Imagination Technologies LimitedInventors: Xile Yang, John W. Howson, Jonathan Redshaw
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Publication number: 20220245755Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Inventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
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Patent number: 11341601Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.Type: GrantFiled: September 24, 2020Date of Patent: May 24, 2022Assignee: Imagination Technologies LimitedInventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
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Publication number: 20220051363Abstract: A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.Type: ApplicationFiled: October 29, 2021Publication date: February 17, 2022Inventors: John Howson, Jonathan Redshaw, Yoong Chert Foo
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Publication number: 20220020206Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.Type: ApplicationFiled: October 1, 2021Publication date: January 20, 2022Inventor: Jonathan Redshaw
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Patent number: 11189004Abstract: A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.Type: GrantFiled: May 6, 2020Date of Patent: November 30, 2021Assignee: Imagination Technologies LimitedInventors: John Howson, Jonathan Redshaw, Yoong Chert Foo
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Patent number: 11164365Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.Type: GrantFiled: November 12, 2020Date of Patent: November 2, 2021Assignee: Imagination Technologies LimitedInventor: Jonathan Redshaw
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Publication number: 20210224123Abstract: A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.Type: ApplicationFiled: April 1, 2021Publication date: July 22, 2021Inventors: Luca Iuliano, Simon Nield, Yoong-Chert Foo, Ollie Mower, Jonathan Redshaw
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Patent number: 11069024Abstract: A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile. A set of two or more tag buffers store the primitive identifiers determined for each of the sample positions in a tile, thereby representing overlapping layers of primitives. A tag control module controls: (i) selection of a tag buffer for the storage of each of the primitive identifiers according to the layering of the primitive identifiers stored in the tag buffers, and (ii) flushing of primitive identifiers from the tag buffers. A texturing engine applies texturing to the primitives identified by the flushed primitive identifiers.Type: GrantFiled: May 5, 2020Date of Patent: July 20, 2021Assignee: Imagination Technologies LimitedInventor: Jonathan Redshaw
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Patent number: 10990448Abstract: A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.Type: GrantFiled: September 17, 2018Date of Patent: April 27, 2021Assignee: Imagination Technologies LimitedInventors: Luca Iuliano, Simon Nield, Yoong-Chert Foo, Ollie Mower, Jonathan Redshaw
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Patent number: 10957097Abstract: An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.Type: GrantFiled: May 28, 2015Date of Patent: March 23, 2021Assignee: Imagination Technologies LimitedInventors: Xile Yang, John W. Howson, Jonathan Redshaw
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Publication number: 20210065438Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.Type: ApplicationFiled: November 12, 2020Publication date: March 4, 2021Inventor: Jonathan Redshaw