Abstract: A fuel cell system comprises a fuel cell main body containing a fuel cell having an anode side at which fuel is reacted, exhaust products arising at the anode side of the fuel cell as a result of the reaction at the anode side. A recirculation passage is located inside the fuel cell main body and recirculates a proportion of the exhaust products directly to the anode side of the fuel cell for reaction at the anode side. The recirculation passage may include an ejector arrangement for mixing fresh fuel with the recirculated exhaust products and may also include a reforming catalyst for partially reforming the mixture in the recirculation passage.

Abstract: A fuel cell system comprises a fuel cell main body containing a fuel cell having an anode side at which fuel is reacted, exhaust products arising at the anode side of the fuel cell as a result of the reaction at the anode side. A recirculation passage is located inside the fuel cell main body and recirculates a proportion of the exhaust products directly to the anode side of the fuel cell for reaction at the anode side. The recirculation passage may include an ejector arrangement for mixing fresh fuel with the recirculated exhaust products and may also include a reforming catalyst for partially reforming the mixture in the recirculation passage.

Abstract: A fuel cell system comprises a fuel cell main body containing a fuel cell having an anode side at which fuel is reacted, exhaust products arising at the anode side of the fuel cell as a result of the reaction at the anode side. A recirculation passage is located inside the fuel cell main body and recirculates a proportion of the exhaust products directly to the anode side of the fuel cell for reaction at the anode side. The recirculation passage may include an ejector arrangement for mixing fresh fuel with the recirculated exhaust products and may also include a reforming catalyst for partially reforming the mixture in the recirculation passage.

Abstract: A parallel processing system computer which utilizes the logic programming language Prolog comprising a plurality of processing nodes, each node comprising three central processing units (CPUs), a memory architecture adapted for Prolog execution and interfacing hardware, each processing node being connected to a communication bus and a real-time broadcast bus whereby the real-time data from an input can be broadcast via the real-time broadcast bus to each processing node. One of the CPUs is used to control the communications and scheduling of the node, the other two CPUs are used as sequential Prolog Processors (SPPS). Each node can be arranged such that the collection of unused memory is carried out by one SPP while another SPP continues to run Prolog program enabling continuous real-time operation. The memory architecture is hybrid and comprises local static RAM and global dynamic RAM. The dynamic RAM comprises a Prolog database of known signal for comparison with the real-time input signals.