Patents by Inventor Jonathan Rullan

Jonathan Rullan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130252417
    Abstract: A thin film forming method in which a thin film is formed on a surface of a target object to be processed to fill a recess formed in the surface of the target object includes the steps of forming a metal layer for filling on the surface of the target object to fill the recess formed in the surface of the target object and forming a metal film for preventing diffusion on an entire surface of the target object to cover the metal layer for filling. The thin film forming method further includes the step of annealing the target object having the metal film for preventing diffusion formed thereon.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 26, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro ISHIZAKA, Jonathan Rullan, Osamu Yokoyama, Atsushi Gomi, Chiaki Yasumuro, Takara Kato, Tatsuo Hatano, Hiroaki Kawasaki
  • Patent number: 7884012
    Abstract: A method is provided for void-free copper (Cu) filling of recessed features in a semiconductor device. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film on the patterned substrate, including in the recessed feature, depositing a Ru metal film on the barrier film, and depositing a discontinuous Cu seed layer on the Ru metal film, where the Cu seed layer partially covers the Ru metal film in the recessed feature. The method further includes exposing the substrate to an oxidation source gas that oxidizes the Cu seed layer and the portion of the Ru metal film not covered by the Cu seed layer, heat-treating the oxidized Cu seed layer and the oxidized Ru metal film under high vacuum conditions or in the presence of an inert gas to activate the oxidized Ru metal film for Cu plating, and filling the recessed feature with bulk Cu metal.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 8, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kenji Suzuki, Tadahiro Ishizaka, Miho Jomen, Jonathan Rullan
  • Patent number: 7776740
    Abstract: A method for integrating low-temperature selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. The method includes providing a patterned substrate containing a recessed feature in a dielectric layer, where the recessed feature is at least substantially filled with planarized bulk Cu metal, heat-treating the bulk Cu metal and the dielectric layer in the presence of H2, N2, or NH3, or a combination thereof, and selectively depositing a Ru metal film on the heat-treated planarized bulk Cu metal.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: August 17, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Kenji Suzuki, Miho Jomen, Jonathan Rullan
  • Publication number: 20090186481
    Abstract: A method for integrating low-temperature selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. The method includes providing a patterned substrate containing a recessed feature in a dielectric layer, where the recessed feature is at least substantially filled with planarized bulk Cu metal, heat-treating the bulk Cu metal and the dielectric layer in the presence of H2, N2, or NH3, or a combination thereof, and selectively depositing a Ru metal film on the heat-treated planarized bulk Cu metal.
    Type: Application
    Filed: January 22, 2008
    Publication date: July 23, 2009
    Inventors: Kenji SUZUKI, Miho JOMEN, Jonathan RULLAN
  • Publication number: 20090087981
    Abstract: A method is provided for void-free copper (Cu) filling of recessed features in a semiconductor device. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film on the patterned substrate, including in the recessed feature, depositing a Ru metal film on the barrier film, and depositing a discontinuous Cu seed layer on the Ru metal film, where the Cu seed layer partially covers the Ru metal film in the recessed feature. The method further includes exposing the substrate to an oxidation source gas that oxidizes the Cu seed layer and the portion of the Ru metal film not covered by the Cu seed layer, heat-treating the oxidized Cu seed layer and the oxidized Ru metal film under high vacuum conditions or in the presence of an inert gas to activate the oxidized Ru metal film for Cu plating, and filling the recessed feature with bulk Cu metal.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kenji Suzuki, Tadahiro Ishizaka, Miho Jomen, Jonathan Rullan