Abstract: A cache memory capable of concurrently accepting and working on completion of more than one cache access from a plurality of processors connected in parallel. Current accesses to the cache are handled by current-access-completion circuitry which determines whether the current access is capable of immediate completion and either completes the access immediately if so capable or transfers the access to pending-access-completion circuitry if not so capable. The latter circuitry works on completion of pending accesses; it determines and stores for each pending access status information prescribing the steps required to complete the access and redetermines that status information as conditions change. In working on completion of current and pending accesses, the addresses of the accesses are compared to those of memory accesses in progress on the system.

Abstract: A data processing system using separate fixed point and floating point computation units and a single control store means for controlling the operations of both units, the units being responsive to commonly shared control fields of the microinstructions supplied from the control store means during their respective operations. The floating point unit can provide single or double precision results, an additional control field of the microinstructions identifying which result is required.

Abstract: A floating point computation unit for use in a data processing system in which the mantissa processing means provides an overall computation result a portion of which represents the desired mantissa result. A carry-in bit is added to the least significant bit of the overall result and is propagated through the mantissa processing means so that it can be added to the least significant bit of the desired mantissa result to provide a rounding of such desired result.

Abstract: A data processing system using unique procedures for handling various arithmetic operations. Thus, in floating point arithmetic mantissa calculations the system uses a novel technique for inserting a round bit into the appropriate bit of the floating point result wherein a look-ahead carry bit generator stage is used for such purpose to reduce the overall mantissa calculation time. Further, the system utilizes unique logic which operates in parallel with the floating point exponent calculation logic for effectively predicting whether or not an overflow or underflow condition will be present in the final exponent result and for informing the system which such conditions have occurred. Moreover, the system utilizes a simplified technique for computing the extension bits which are required in multiply and divide computations wherein a programmable array logic unit and a four-bit adder unit are combined for such purposes.

Abstract: A data processing system using unique procedures for handling various arithmetic operations. Thus, in floating point arithmetic mantissa calculations the system uses a novel technique for inserting a round bit into the appropriate bit of the floating point result wherein a look-ahead carry bit generator stage is used for such purpose to reduce the overall mantissa calculation time. Further, the system utilizes unique logic which operates in parallel with the floating point exponent calculation logic for effectively predicting whether or not an overflow or underflow condition will be present in the final exponent result and for informing the system which such conditions have occurred. Moreover, the system utilizes a simplified technique for computing the extension bits which are required in multiply and divide computations wherein a programmable array logic unit and a four-bit adder unit are combined for such purposes.