Abstract: Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.

Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.

Abstract: A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.

Abstract: An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.

Abstract: A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.

Abstract: Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.

Abstract: An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.

Abstract: A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.

Abstract: A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.

Abstract: A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.

Abstract: A protection circuit is designed with an external terminal (300), a reference terminal (126) and a substrate (342). A semiconductor body (338) is formed by an isolation region (332, 340) formed between the substrate and the semiconductor body, thereby enclosing the semiconductor body. A plurality of transistors is formed in the semiconductor body. Each transistor has a respective control terminal (354) connected to a common control terminal (321) and a respective current path connected between the external terminal and the reference terminal. A capacitor (314) is connected between the semiconductor body and the external terminal. A resistor (318) is connected between the semiconductor body and the reference terminal.